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core: Send FPU interrupts to writeback rather than execute1
[microwatt.git] / soc.vhdl
1 library ieee;
2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
4 use ieee.math_real.all;
5 use std.textio.all;
6 use std.env.stop;
7
8 library work;
9 use work.common.all;
10 use work.wishbone_types.all;
11
12
13 -- Memory map. *** Keep include/microwatt_soc.h updated on changes ***
14 --
15 -- Main bus:
16 -- 0x00000000: Block RAM (MEMORY_SIZE) or DRAM depending on syscon
17 -- 0x40000000: DRAM (when present)
18 -- 0x80000000: Block RAM (aliased & repeated)
19
20 -- IO Bus:
21 -- 0xc0000000: SYSCON
22 -- 0xc0002000: UART0
23 -- 0xc0003000: UART1 (if any)
24 -- 0xc0004000: XICS ICP
25 -- 0xc0005000: XICS ICS
26 -- 0xc0006000: SPI Flash controller
27 -- 0xc8nnnnnn: External IO bus
28 -- 0xf0000000: Flash "ROM" mapping
29 -- 0xff000000: DRAM init code (if any) or flash ROM (**)
30
31 -- External IO bus:
32 -- 0xc8000000: LiteDRAM control (CSRs)
33 -- 0xc8020000: LiteEth CSRs (*)
34 -- 0xc8030000: LiteEth MMIO (*)
35
36 -- (*) LiteEth must be a single aligned 32KB block as the CSRs and MMIOs
37 -- are actually decoded as a single wishbone which LiteEth will
38 -- internally split based on bit 16.
39
40 -- (**) DRAM init code is currently special and goes to the external
41 -- IO bus, this will be fixed when it's moved out of litedram and
42 -- into the main SoC once we have a common "firmware".
43
44 -- Interrupt numbers:
45 --
46 -- 0 : UART0
47 -- 1 : Ethernet
48
49 entity soc is
50 generic (
51 MEMORY_SIZE : natural;
52 RAM_INIT_FILE : string;
53 CLK_FREQ : positive;
54 SIM : boolean;
55 HAS_FPU : boolean := true;
56 HAS_BTC : boolean := true;
57 DISABLE_FLATTEN_CORE : boolean := false;
58 HAS_DRAM : boolean := false;
59 DRAM_SIZE : integer := 0;
60 DRAM_INIT_SIZE : integer := 0;
61 HAS_SPI_FLASH : boolean := false;
62 SPI_FLASH_DLINES : positive := 1;
63 SPI_FLASH_OFFSET : integer := 0;
64 SPI_FLASH_DEF_CKDV : natural := 2;
65 SPI_FLASH_DEF_QUAD : boolean := false;
66 LOG_LENGTH : natural := 512;
67 HAS_LITEETH : boolean := false;
68 UART0_IS_16550 : boolean := true;
69 HAS_UART1 : boolean := false
70 );
71 port(
72 rst : in std_ulogic;
73 system_clk : in std_ulogic;
74
75 -- "Large" (64-bit) DRAM wishbone
76 wb_dram_in : out wishbone_master_out;
77 wb_dram_out : in wishbone_slave_out := wishbone_slave_out_init;
78
79 -- "Small" (32-bit) external IO wishbone
80 wb_ext_io_in : out wb_io_master_out;
81 wb_ext_io_out : in wb_io_slave_out := wb_io_slave_out_init;
82 wb_ext_is_dram_csr : out std_ulogic;
83 wb_ext_is_dram_init : out std_ulogic;
84 wb_ext_is_eth : out std_ulogic;
85
86 -- External interrupts
87 ext_irq_eth : in std_ulogic := '0';
88
89 -- UART0 signals:
90 uart0_txd : out std_ulogic;
91 uart0_rxd : in std_ulogic := '0';
92
93 -- UART1 signals:
94 uart1_txd : out std_ulogic;
95 uart1_rxd : in std_ulogic := '0';
96
97 -- SPI Flash signals
98 spi_flash_sck : out std_ulogic;
99 spi_flash_cs_n : out std_ulogic;
100 spi_flash_sdat_o : out std_ulogic_vector(SPI_FLASH_DLINES-1 downto 0);
101 spi_flash_sdat_oe : out std_ulogic_vector(SPI_FLASH_DLINES-1 downto 0);
102 spi_flash_sdat_i : in std_ulogic_vector(SPI_FLASH_DLINES-1 downto 0) := (others => '1');
103
104 -- DRAM controller signals
105 alt_reset : in std_ulogic := '0'
106 );
107 end entity soc;
108
109 architecture behaviour of soc is
110
111 -- Wishbone master signals:
112 signal wishbone_dcore_in : wishbone_slave_out;
113 signal wishbone_dcore_out : wishbone_master_out;
114 signal wishbone_icore_in : wishbone_slave_out;
115 signal wishbone_icore_out : wishbone_master_out;
116 signal wishbone_debug_in : wishbone_slave_out;
117 signal wishbone_debug_out : wishbone_master_out;
118
119 -- Arbiter array (ghdl doesnt' support assigning the array
120 -- elements in the entity instantiation)
121 constant NUM_WB_MASTERS : positive := 3;
122 signal wb_masters_out : wishbone_master_out_vector(0 to NUM_WB_MASTERS-1);
123 signal wb_masters_in : wishbone_slave_out_vector(0 to NUM_WB_MASTERS-1);
124
125 -- Wishbone master (output of arbiter):
126 signal wb_master_in : wishbone_slave_out;
127 signal wb_master_out : wishbone_master_out;
128
129 -- Main "IO" bus, from main slave decoder to the latch
130 signal wb_io_in : wishbone_master_out;
131 signal wb_io_out : wishbone_slave_out;
132
133 -- Secondary (smaller) IO bus after the IO bus latch
134 signal wb_sio_out : wb_io_master_out;
135 signal wb_sio_in : wb_io_slave_out;
136
137 -- Syscon signals
138 signal dram_at_0 : std_ulogic;
139 signal do_core_reset : std_ulogic;
140 signal wb_syscon_in : wb_io_master_out;
141 signal wb_syscon_out : wb_io_slave_out;
142
143 -- UART0 signals:
144 signal wb_uart0_in : wb_io_master_out;
145 signal wb_uart0_out : wb_io_slave_out;
146 signal uart0_dat8 : std_ulogic_vector(7 downto 0);
147 signal uart0_irq : std_ulogic;
148
149 -- UART1 signals:
150 signal wb_uart1_in : wb_io_master_out;
151 signal wb_uart1_out : wb_io_slave_out;
152 signal uart1_dat8 : std_ulogic_vector(7 downto 0);
153 signal uart1_irq : std_ulogic;
154
155 -- SPI Flash controller signals:
156 signal wb_spiflash_in : wb_io_master_out;
157 signal wb_spiflash_out : wb_io_slave_out;
158 signal wb_spiflash_is_reg : std_ulogic;
159 signal wb_spiflash_is_map : std_ulogic;
160
161 -- XICS signals:
162 signal wb_xics_icp_in : wb_io_master_out;
163 signal wb_xics_icp_out : wb_io_slave_out;
164 signal wb_xics_ics_in : wb_io_master_out;
165 signal wb_xics_ics_out : wb_io_slave_out;
166 signal int_level_in : std_ulogic_vector(15 downto 0);
167 signal ics_to_icp : ics_to_icp_t;
168 signal core_ext_irq : std_ulogic;
169
170 -- Main memory signals:
171 signal wb_bram_in : wishbone_master_out;
172 signal wb_bram_out : wishbone_slave_out;
173
174 -- DMI debug bus signals
175 signal dmi_addr : std_ulogic_vector(7 downto 0);
176 signal dmi_din : std_ulogic_vector(63 downto 0);
177 signal dmi_dout : std_ulogic_vector(63 downto 0);
178 signal dmi_req : std_ulogic;
179 signal dmi_wr : std_ulogic;
180 signal dmi_ack : std_ulogic;
181
182 -- Per slave DMI signals
183 signal dmi_wb_dout : std_ulogic_vector(63 downto 0);
184 signal dmi_wb_req : std_ulogic;
185 signal dmi_wb_ack : std_ulogic;
186 signal dmi_core_dout : std_ulogic_vector(63 downto 0);
187 signal dmi_core_req : std_ulogic;
188 signal dmi_core_ack : std_ulogic;
189
190 -- Delayed/latched resets and alt_reset
191 signal rst_core : std_ulogic := '1';
192 signal rst_uart : std_ulogic := '1';
193 signal rst_xics : std_ulogic := '1';
194 signal rst_spi : std_ulogic := '1';
195 signal rst_bram : std_ulogic := '1';
196 signal rst_dtm : std_ulogic := '1';
197 signal rst_wbar : std_ulogic := '1';
198 signal rst_wbdb : std_ulogic := '1';
199 signal alt_reset_d : std_ulogic;
200
201 -- IO branch split:
202 type slave_io_type is (SLAVE_IO_SYSCON,
203 SLAVE_IO_UART,
204 SLAVE_IO_ICP,
205 SLAVE_IO_ICS,
206 SLAVE_IO_UART1,
207 SLAVE_IO_SPI_FLASH_REG,
208 SLAVE_IO_SPI_FLASH_MAP,
209 SLAVE_IO_EXTERNAL,
210 SLAVE_IO_NONE);
211 signal slave_io_dbg : slave_io_type;
212
213 -- This is the component exported by the 16550 compatible
214 -- UART from FuseSoC.
215 --
216 component uart_top port (
217 wb_clk_i : in std_ulogic;
218 wb_rst_i : in std_ulogic;
219 wb_adr_i : in std_ulogic_vector(2 downto 0);
220 wb_dat_i : in std_ulogic_vector(7 downto 0);
221 wb_dat_o : out std_ulogic_vector(7 downto 0);
222 wb_we_i : in std_ulogic;
223 wb_stb_i : in std_ulogic;
224 wb_cyc_i : in std_ulogic;
225 wb_ack_o : out std_ulogic;
226 int_o : out std_ulogic;
227 stx_pad_o : out std_ulogic;
228 srx_pad_i : in std_ulogic;
229 rts_pad_o : out std_ulogic;
230 cts_pad_i : in std_ulogic;
231 dtr_pad_o : out std_ulogic;
232 dsr_pad_i : in std_ulogic;
233 ri_pad_i : in std_ulogic;
234 dcd_pad_i : in std_ulogic
235 );
236 end component;
237 begin
238
239 resets: process(system_clk)
240 begin
241 if rising_edge(system_clk) then
242 rst_core <= rst or do_core_reset;
243 rst_uart <= rst;
244 rst_spi <= rst;
245 rst_xics <= rst;
246 rst_bram <= rst;
247 rst_dtm <= rst;
248 rst_wbar <= rst;
249 rst_wbdb <= rst;
250 alt_reset_d <= alt_reset;
251 end if;
252 end process;
253
254 -- Processor core
255 processor: entity work.core
256 generic map(
257 SIM => SIM,
258 HAS_FPU => HAS_FPU,
259 HAS_BTC => HAS_BTC,
260 DISABLE_FLATTEN => DISABLE_FLATTEN_CORE,
261 ALT_RESET_ADDRESS => (23 downto 0 => '0', others => '1'),
262 LOG_LENGTH => LOG_LENGTH
263 )
264 port map(
265 clk => system_clk,
266 rst => rst_core,
267 alt_reset => alt_reset_d,
268 wishbone_insn_in => wishbone_icore_in,
269 wishbone_insn_out => wishbone_icore_out,
270 wishbone_data_in => wishbone_dcore_in,
271 wishbone_data_out => wishbone_dcore_out,
272 dmi_addr => dmi_addr(3 downto 0),
273 dmi_dout => dmi_core_dout,
274 dmi_din => dmi_dout,
275 dmi_wr => dmi_wr,
276 dmi_ack => dmi_core_ack,
277 dmi_req => dmi_core_req,
278 ext_irq => core_ext_irq
279 );
280
281 -- Wishbone bus master arbiter & mux
282 wb_masters_out <= (0 => wishbone_dcore_out,
283 1 => wishbone_icore_out,
284 2 => wishbone_debug_out);
285 wishbone_dcore_in <= wb_masters_in(0);
286 wishbone_icore_in <= wb_masters_in(1);
287 wishbone_debug_in <= wb_masters_in(2);
288 wishbone_arbiter_0: entity work.wishbone_arbiter
289 generic map(
290 NUM_MASTERS => NUM_WB_MASTERS
291 )
292 port map(
293 clk => system_clk,
294 rst => rst_wbar,
295 wb_masters_in => wb_masters_out,
296 wb_masters_out => wb_masters_in,
297 wb_slave_out => wb_master_out,
298 wb_slave_in => wb_master_in
299 );
300
301 -- Top level Wishbone slaves address decoder & mux
302 --
303 -- From CPU to BRAM, DRAM, IO, selected on top 3 bits and dram_at_0
304 -- 0000 - BRAM
305 -- 0001 - DRAM
306 -- 01xx - DRAM
307 -- 10xx - BRAM
308 -- 11xx - IO
309 --
310 slave_top_intercon: process(wb_master_out, wb_bram_out, wb_dram_out, wb_io_out, dram_at_0)
311 type slave_top_type is (SLAVE_TOP_BRAM,
312 SLAVE_TOP_DRAM,
313 SLAVE_TOP_IO);
314 variable slave_top : slave_top_type;
315 variable top_decode : std_ulogic_vector(3 downto 0);
316 begin
317 -- Top-level address decoder
318 top_decode := wb_master_out.adr(31 downto 29) & dram_at_0;
319 slave_top := SLAVE_TOP_BRAM;
320 if std_match(top_decode, "0000") then
321 slave_top := SLAVE_TOP_BRAM;
322 elsif std_match(top_decode, "0001") then
323 slave_top := SLAVE_TOP_DRAM;
324 elsif std_match(top_decode, "01--") then
325 slave_top := SLAVE_TOP_DRAM;
326 elsif std_match(top_decode, "10--") then
327 slave_top := SLAVE_TOP_BRAM;
328 elsif std_match(top_decode, "11--") then
329 slave_top := SLAVE_TOP_IO;
330 end if;
331
332 -- Top level wishbone muxing.
333 wb_bram_in <= wb_master_out;
334 wb_bram_in.cyc <= '0';
335 wb_dram_in <= wb_master_out;
336 wb_dram_in.cyc <= '0';
337 wb_io_in <= wb_master_out;
338 wb_io_in.cyc <= '0';
339 case slave_top is
340 when SLAVE_TOP_BRAM =>
341 wb_bram_in.cyc <= wb_master_out.cyc;
342 wb_master_in <= wb_bram_out;
343 when SLAVE_TOP_DRAM =>
344 if HAS_DRAM then
345 wb_dram_in.cyc <= wb_master_out.cyc;
346 wb_master_in <= wb_dram_out;
347 else
348 wb_master_in.ack <= wb_master_out.cyc and wb_master_out.stb;
349 wb_master_in.dat <= (others => '1');
350 wb_master_in.stall <= '0';
351 end if;
352 when SLAVE_TOP_IO =>
353 wb_io_in.cyc <= wb_master_out.cyc;
354 wb_master_in <= wb_io_out;
355 end case;
356
357 end process slave_top_intercon;
358
359 -- IO wishbone slave 64->32 bits converter
360 --
361 -- For timing reasons, this adds a one cycle latch on the way both
362 -- in and out. This relaxes timing and routing pressure on the "main"
363 -- memory bus by moving all simple IOs to a slower 32-bit bus.
364 --
365 -- This implementation is rather dumb at the moment, no stash buffer,
366 -- so we stall whenever that latch is busy. This can be improved.
367 --
368 slave_io_latch: process(system_clk)
369 -- State
370 type state_t is (IDLE, WAIT_ACK_BOT, WAIT_ACK_TOP);
371 variable state : state_t;
372
373 -- Misc
374 variable has_top : boolean;
375 variable has_bot : boolean;
376 begin
377 if rising_edge(system_clk) then
378 if (rst) then
379 state := IDLE;
380 wb_io_out.ack <= '0';
381 wb_io_out.stall <= '0';
382 wb_sio_out.cyc <= '0';
383 wb_sio_out.stb <= '0';
384 has_top := false;
385 has_bot := false;
386 else
387 case state is
388 when IDLE =>
389 -- Clear ACK in case it was set
390 wb_io_out.ack <= '0';
391
392 -- Do we have a cycle ?
393 if wb_io_in.cyc = '1' and wb_io_in.stb = '1' then
394 -- Stall master until we are done, we are't (yet) pipelining
395 -- this, it's all slow IOs.
396 wb_io_out.stall <= '1';
397
398 -- Start cycle downstream
399 wb_sio_out.cyc <= '1';
400 wb_sio_out.stb <= '1';
401
402 -- Copy write enable to IO out, copy address as well
403 wb_sio_out.we <= wb_io_in.we;
404 wb_sio_out.adr <= wb_io_in.adr(wb_sio_out.adr'left downto 3) & "000";
405
406 -- Do we have a top word and/or a bottom word ?
407 has_top := wb_io_in.sel(7 downto 4) /= "0000";
408 has_bot := wb_io_in.sel(3 downto 0) /= "0000";
409
410 -- If we have a bottom word, handle it first, otherwise
411 -- send the top word down. XXX Split the actual mux out
412 -- and only generate a control signal.
413 if has_bot then
414 if wb_io_in.we = '1' then
415 wb_sio_out.dat <= wb_io_in.dat(31 downto 0);
416 end if;
417 wb_sio_out.sel <= wb_io_in.sel(3 downto 0);
418
419 -- Wait for ack
420 state := WAIT_ACK_BOT;
421 else
422 if wb_io_in.we = '1' then
423 wb_sio_out.dat <= wb_io_in.dat(63 downto 32);
424 end if;
425 wb_sio_out.sel <= wb_io_in.sel(7 downto 4);
426
427 -- Bump address
428 wb_sio_out.adr(2) <= '1';
429
430 -- Wait for ack
431 state := WAIT_ACK_TOP;
432 end if;
433 end if;
434 when WAIT_ACK_BOT =>
435 -- If we aren't stalled by the device, clear stb
436 if wb_sio_in.stall = '0' then
437 wb_sio_out.stb <= '0';
438 end if;
439
440 -- Handle ack
441 if wb_sio_in.ack = '1' then
442 -- If it's a read, latch the data
443 if wb_sio_out.we = '0' then
444 wb_io_out.dat(31 downto 0) <= wb_sio_in.dat;
445 end if;
446
447 -- Do we have a "top" part as well ?
448 if has_top then
449 -- Latch data & sel
450 if wb_io_in.we = '1' then
451 wb_sio_out.dat <= wb_io_in.dat(63 downto 32);
452 end if;
453 wb_sio_out.sel <= wb_io_in.sel(7 downto 4);
454
455 -- Bump address and set STB
456 wb_sio_out.adr(2) <= '1';
457 wb_sio_out.stb <= '1';
458
459 -- Wait for new ack
460 state := WAIT_ACK_TOP;
461 else
462 -- We are done, ack up, clear cyc downstram
463 wb_sio_out.cyc <= '0';
464
465 -- And ack & unstall upstream
466 wb_io_out.ack <= '1';
467 wb_io_out.stall <= '0';
468
469 -- Wait for next one
470 state := IDLE;
471 end if;
472 end if;
473 when WAIT_ACK_TOP =>
474 -- If we aren't stalled by the device, clear stb
475 if wb_sio_in.stall = '0' then
476 wb_sio_out.stb <= '0';
477 end if;
478
479 -- Handle ack
480 if wb_sio_in.ack = '1' then
481 -- If it's a read, latch the data
482 if wb_sio_out.we = '0' then
483 wb_io_out.dat(63 downto 32) <= wb_sio_in.dat;
484 end if;
485
486 -- We are done, ack up, clear cyc downstram
487 wb_sio_out.cyc <= '0';
488
489 -- And ack & unstall upstream
490 wb_io_out.ack <= '1';
491 wb_io_out.stall <= '0';
492
493 -- Wait for next one
494 state := IDLE;
495 end if;
496 end case;
497 end if;
498 end if;
499 end process;
500
501 -- IO wishbone slave intercon.
502 --
503 slave_io_intercon: process(wb_sio_out, wb_syscon_out, wb_uart0_out, wb_uart1_out,
504 wb_ext_io_out, wb_xics_icp_out, wb_xics_ics_out,
505 wb_spiflash_out)
506 variable slave_io : slave_io_type;
507
508 variable match : std_ulogic_vector(31 downto 12);
509 variable ext_valid : boolean;
510 begin
511
512 -- Simple address decoder.
513 slave_io := SLAVE_IO_NONE;
514 match := "11" & wb_sio_out.adr(29 downto 12);
515 if std_match(match, x"FF---") and HAS_DRAM then
516 slave_io := SLAVE_IO_EXTERNAL;
517 elsif std_match(match, x"F----") then
518 slave_io := SLAVE_IO_SPI_FLASH_MAP;
519 elsif std_match(match, x"C0000") then
520 slave_io := SLAVE_IO_SYSCON;
521 elsif std_match(match, x"C0002") then
522 slave_io := SLAVE_IO_UART;
523 elsif std_match(match, x"C0003") then
524 slave_io := SLAVE_IO_UART1;
525 elsif std_match(match, x"C8---") then
526 slave_io := SLAVE_IO_EXTERNAL;
527 elsif std_match(match, x"C0004") then
528 slave_io := SLAVE_IO_ICP;
529 elsif std_match(match, x"C0005") then
530 slave_io := SLAVE_IO_ICS;
531 elsif std_match(match, x"C0006") then
532 slave_io := SLAVE_IO_SPI_FLASH_REG;
533 end if;
534 slave_io_dbg <= slave_io;
535 wb_uart0_in <= wb_sio_out;
536 wb_uart0_in.cyc <= '0';
537 wb_uart1_in <= wb_sio_out;
538 wb_uart1_in.cyc <= '0';
539 wb_spiflash_in <= wb_sio_out;
540 wb_spiflash_in.cyc <= '0';
541 wb_spiflash_is_reg <= '0';
542 wb_spiflash_is_map <= '0';
543
544 -- Only give xics 8 bits of wb addr (for now...)
545 wb_xics_icp_in <= wb_sio_out;
546 wb_xics_icp_in.adr <= (others => '0');
547 wb_xics_icp_in.adr(7 downto 0) <= wb_sio_out.adr(7 downto 0);
548 wb_xics_icp_in.cyc <= '0';
549 wb_xics_ics_in <= wb_sio_out;
550 wb_xics_ics_in.adr <= (others => '0');
551 wb_xics_ics_in.adr(11 downto 0) <= wb_sio_out.adr(11 downto 0);
552 wb_xics_ics_in.cyc <= '0';
553
554 wb_ext_io_in <= wb_sio_out;
555 wb_ext_io_in.cyc <= '0';
556
557 wb_syscon_in <= wb_sio_out;
558 wb_syscon_in.cyc <= '0';
559
560 wb_ext_is_dram_csr <= '0';
561 wb_ext_is_dram_init <= '0';
562 wb_ext_is_eth <= '0';
563
564 -- Default response, ack & return all 1's
565 wb_sio_in.dat <= (others => '1');
566 wb_sio_in.ack <= wb_sio_out.stb and wb_sio_out.cyc;
567 wb_sio_in.stall <= '0';
568
569 case slave_io is
570 when SLAVE_IO_EXTERNAL =>
571 -- Ext IO "chip selects"
572 --
573 -- DRAM init is special at 0xFF* so we just test the top
574 -- bit. Everything else is at 0xC8* so we test only bits
575 -- 23 downto 16.
576 --
577 ext_valid := false;
578 if wb_sio_out.adr(29) = '1' and HAS_DRAM then -- DRAM init is special
579 wb_ext_is_dram_init <= '1';
580 ext_valid := true;
581 elsif wb_sio_out.adr(23 downto 16) = x"00" and HAS_DRAM then
582 wb_ext_is_dram_csr <= '1';
583 ext_valid := true;
584 elsif wb_sio_out.adr(23 downto 16) = x"02" and HAS_LITEETH then
585 wb_ext_is_eth <= '1';
586 ext_valid := true;
587 elsif wb_sio_out.adr(23 downto 16) = x"03" and HAS_LITEETH then
588 wb_ext_is_eth <= '1';
589 ext_valid := true;
590 end if;
591 if ext_valid then
592 wb_ext_io_in.cyc <= wb_sio_out.cyc;
593 wb_sio_in <= wb_ext_io_out;
594 end if;
595
596 when SLAVE_IO_SYSCON =>
597 wb_syscon_in.cyc <= wb_sio_out.cyc;
598 wb_sio_in <= wb_syscon_out;
599 when SLAVE_IO_UART =>
600 wb_uart0_in.cyc <= wb_sio_out.cyc;
601 wb_sio_in <= wb_uart0_out;
602 when SLAVE_IO_ICP =>
603 wb_xics_icp_in.cyc <= wb_sio_out.cyc;
604 wb_sio_in <= wb_xics_icp_out;
605 when SLAVE_IO_ICS =>
606 wb_xics_ics_in.cyc <= wb_sio_out.cyc;
607 wb_sio_in <= wb_xics_ics_out;
608 when SLAVE_IO_UART1 =>
609 wb_uart1_in.cyc <= wb_sio_out.cyc;
610 wb_sio_in <= wb_uart1_out;
611 when SLAVE_IO_SPI_FLASH_MAP =>
612 -- Clear top bits so they don't make their way to the
613 -- fash chip.
614 wb_spiflash_in.adr(29 downto 28) <= "00";
615 wb_spiflash_in.cyc <= wb_sio_out.cyc;
616 wb_sio_in <= wb_spiflash_out;
617 wb_spiflash_is_map <= '1';
618 when SLAVE_IO_SPI_FLASH_REG =>
619 wb_spiflash_in.cyc <= wb_sio_out.cyc;
620 wb_sio_in <= wb_spiflash_out;
621 wb_spiflash_is_reg <= '1';
622 when others =>
623 end case;
624
625 end process;
626
627 -- Syscon slave
628 syscon0: entity work.syscon
629 generic map(
630 HAS_UART => true,
631 HAS_DRAM => HAS_DRAM,
632 BRAM_SIZE => MEMORY_SIZE,
633 DRAM_SIZE => DRAM_SIZE,
634 DRAM_INIT_SIZE => DRAM_INIT_SIZE,
635 CLK_FREQ => CLK_FREQ,
636 HAS_SPI_FLASH => HAS_SPI_FLASH,
637 SPI_FLASH_OFFSET => SPI_FLASH_OFFSET,
638 HAS_LITEETH => HAS_LITEETH,
639 UART0_IS_16550 => UART0_IS_16550,
640 HAS_UART1 => HAS_UART1
641 )
642 port map(
643 clk => system_clk,
644 rst => rst,
645 wishbone_in => wb_syscon_in,
646 wishbone_out => wb_syscon_out,
647 dram_at_0 => dram_at_0,
648 core_reset => do_core_reset,
649 soc_reset => open -- XXX TODO
650 );
651
652 --
653 -- UART0
654 --
655 -- Either potato (legacy) or 16550
656 --
657 uart0_pp: if not UART0_IS_16550 generate
658 uart0: entity work.pp_soc_uart
659 generic map(
660 FIFO_DEPTH => 32
661 )
662 port map(
663 clk => system_clk,
664 reset => rst_uart,
665 txd => uart0_txd,
666 rxd => uart0_rxd,
667 irq => uart0_irq,
668 wb_adr_in => wb_uart0_in.adr(11 downto 0),
669 wb_dat_in => wb_uart0_in.dat(7 downto 0),
670 wb_dat_out => uart0_dat8,
671 wb_cyc_in => wb_uart0_in.cyc,
672 wb_stb_in => wb_uart0_in.stb,
673 wb_we_in => wb_uart0_in.we,
674 wb_ack_out => wb_uart0_out.ack
675 );
676 end generate;
677
678 uart0_16550 : if UART0_IS_16550 generate
679 signal irq_l : std_ulogic;
680 begin
681 uart0: uart_top
682 port map (
683 wb_clk_i => system_clk,
684 wb_rst_i => rst_uart,
685 wb_adr_i => wb_uart0_in.adr(4 downto 2),
686 wb_dat_i => wb_uart0_in.dat(7 downto 0),
687 wb_dat_o => uart0_dat8,
688 wb_we_i => wb_uart0_in.we,
689 wb_stb_i => wb_uart0_in.stb,
690 wb_cyc_i => wb_uart0_in.cyc,
691 wb_ack_o => wb_uart0_out.ack,
692 int_o => irq_l,
693 stx_pad_o => uart0_txd,
694 srx_pad_i => uart0_rxd,
695 rts_pad_o => open,
696 cts_pad_i => '1',
697 dtr_pad_o => open,
698 dsr_pad_i => '1',
699 ri_pad_i => '0',
700 dcd_pad_i => '1'
701 );
702
703 -- Add a register on the irq out, helps timing
704 uart0_irq_latch: process(system_clk)
705 begin
706 if rising_edge(system_clk) then
707 uart0_irq <= irq_l;
708 end if;
709 end process;
710 end generate;
711
712 wb_uart0_out.dat <= x"000000" & uart0_dat8;
713 wb_uart0_out.stall <= not wb_uart0_out.ack;
714
715 --
716 -- UART1
717 --
718 -- Always 16550 if it exists
719 --
720 uart1: if HAS_UART1 generate
721 signal irq_l : std_ulogic;
722 begin
723 uart1: uart_top
724 port map (
725 wb_clk_i => system_clk,
726 wb_rst_i => rst_uart,
727 wb_adr_i => wb_uart1_in.adr(4 downto 2),
728 wb_dat_i => wb_uart1_in.dat(7 downto 0),
729 wb_dat_o => uart1_dat8,
730 wb_we_i => wb_uart1_in.we,
731 wb_stb_i => wb_uart1_in.stb,
732 wb_cyc_i => wb_uart1_in.cyc,
733 wb_ack_o => wb_uart1_out.ack,
734 int_o => irq_l,
735 stx_pad_o => uart1_txd,
736 srx_pad_i => uart1_rxd,
737 rts_pad_o => open,
738 cts_pad_i => '1',
739 dtr_pad_o => open,
740 dsr_pad_i => '1',
741 ri_pad_i => '0',
742 dcd_pad_i => '1'
743 );
744 -- Add a register on the irq out, helps timing
745 uart0_irq_latch: process(system_clk)
746 begin
747 if rising_edge(system_clk) then
748 uart1_irq <= irq_l;
749 end if;
750 end process;
751 wb_uart1_out.dat <= x"000000" & uart1_dat8;
752 wb_uart1_out.stall <= not wb_uart1_out.ack;
753 end generate;
754
755 no_uart1 : if not HAS_UART1 generate
756 wb_uart1_out.dat <= x"00000000";
757 wb_uart1_out.ack <= wb_uart1_in.cyc and wb_uart1_in.stb;
758 wb_uart1_out.stall <= '0';
759 uart1_irq <= '0';
760 end generate;
761
762 spiflash_gen: if HAS_SPI_FLASH generate
763 spiflash: entity work.spi_flash_ctrl
764 generic map (
765 DATA_LINES => SPI_FLASH_DLINES,
766 DEF_CLK_DIV => SPI_FLASH_DEF_CKDV,
767 DEF_QUAD_READ => SPI_FLASH_DEF_QUAD
768 )
769 port map(
770 rst => rst_spi,
771 clk => system_clk,
772 wb_in => wb_spiflash_in,
773 wb_out => wb_spiflash_out,
774 wb_sel_reg => wb_spiflash_is_reg,
775 wb_sel_map => wb_spiflash_is_map,
776 sck => spi_flash_sck,
777 cs_n => spi_flash_cs_n,
778 sdat_o => spi_flash_sdat_o,
779 sdat_oe => spi_flash_sdat_oe,
780 sdat_i => spi_flash_sdat_i
781 );
782 end generate;
783
784 no_spi0_gen: if not HAS_SPI_FLASH generate
785 wb_spiflash_out.dat <= (others => '1');
786 wb_spiflash_out.ack <= wb_spiflash_in.cyc and wb_spiflash_in.stb;
787 wb_spiflash_out.stall <= wb_spiflash_in.cyc and not wb_spiflash_out.ack;
788 end generate;
789
790 xics_icp: entity work.xics_icp
791 port map(
792 clk => system_clk,
793 rst => rst_xics,
794 wb_in => wb_xics_icp_in,
795 wb_out => wb_xics_icp_out,
796 ics_in => ics_to_icp,
797 core_irq_out => core_ext_irq
798 );
799
800 xics_ics: entity work.xics_ics
801 generic map(
802 SRC_NUM => 16,
803 PRIO_BITS => 3
804 )
805 port map(
806 clk => system_clk,
807 rst => rst_xics,
808 wb_in => wb_xics_ics_in,
809 wb_out => wb_xics_ics_out,
810 int_level_in => int_level_in,
811 icp_out => ics_to_icp
812 );
813
814 -- Assign external interrupts
815 interrupts: process(all)
816 begin
817 int_level_in <= (others => '0');
818 int_level_in(0) <= uart0_irq;
819 int_level_in(1) <= ext_irq_eth;
820 int_level_in(2) <= uart1_irq;
821 end process;
822
823 -- BRAM Memory slave
824 bram: if MEMORY_SIZE /= 0 generate
825 bram0: entity work.wishbone_bram_wrapper
826 generic map(
827 MEMORY_SIZE => MEMORY_SIZE,
828 RAM_INIT_FILE => RAM_INIT_FILE
829 )
830 port map(
831 clk => system_clk,
832 rst => rst_bram,
833 wishbone_in => wb_bram_in,
834 wishbone_out => wb_bram_out
835 );
836 end generate;
837
838 no_bram: if MEMORY_SIZE = 0 generate
839 wb_bram_out.ack <= wb_bram_in.cyc and wb_bram_in.stb;
840 wb_bram_out.dat <= x"FFFFFFFFFFFFFFFF";
841 wb_bram_out.stall <= not wb_bram_out.ack;
842 end generate;
843
844 -- DMI(debug bus) <-> JTAG bridge
845 dtm: entity work.dmi_dtm
846 generic map(
847 ABITS => 8,
848 DBITS => 64
849 )
850 port map(
851 sys_clk => system_clk,
852 sys_reset => rst_dtm,
853 dmi_addr => dmi_addr,
854 dmi_din => dmi_din,
855 dmi_dout => dmi_dout,
856 dmi_req => dmi_req,
857 dmi_wr => dmi_wr,
858 dmi_ack => dmi_ack
859 );
860
861 -- DMI interconnect
862 dmi_intercon: process(dmi_addr, dmi_req,
863 dmi_wb_ack, dmi_wb_dout,
864 dmi_core_ack, dmi_core_dout)
865
866 -- DMI address map (each address is a full 64-bit register)
867 --
868 -- Offset: Size: Slave:
869 -- 0 4 Wishbone
870 -- 10 16 Core
871
872 type slave_type is (SLAVE_WB,
873 SLAVE_CORE,
874 SLAVE_NONE);
875 variable slave : slave_type;
876 begin
877 -- Simple address decoder
878 slave := SLAVE_NONE;
879 if std_match(dmi_addr, "000000--") then
880 slave := SLAVE_WB;
881 elsif std_match(dmi_addr, "0001----") then
882 slave := SLAVE_CORE;
883 end if;
884
885 -- DMI muxing
886 dmi_wb_req <= '0';
887 dmi_core_req <= '0';
888 case slave is
889 when SLAVE_WB =>
890 dmi_wb_req <= dmi_req;
891 dmi_ack <= dmi_wb_ack;
892 dmi_din <= dmi_wb_dout;
893 when SLAVE_CORE =>
894 dmi_core_req <= dmi_req;
895 dmi_ack <= dmi_core_ack;
896 dmi_din <= dmi_core_dout;
897 when others =>
898 dmi_ack <= dmi_req;
899 dmi_din <= (others => '1');
900 end case;
901
902 -- SIM magic exit
903 if SIM and dmi_req = '1' and dmi_addr = "11111111" and dmi_wr = '1' then
904 stop;
905 end if;
906 end process;
907
908 -- Wishbone debug master (TODO: Add a DMI address decoder)
909 wishbone_debug: entity work.wishbone_debug_master
910 port map(clk => system_clk,
911 rst => rst_wbdb,
912 dmi_addr => dmi_addr(1 downto 0),
913 dmi_dout => dmi_wb_dout,
914 dmi_din => dmi_dout,
915 dmi_wr => dmi_wr,
916 dmi_ack => dmi_wb_ack,
917 dmi_req => dmi_wb_req,
918 wb_in => wishbone_debug_in,
919 wb_out => wishbone_debug_out);
920
921
922 end architecture behaviour;