2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
6 use work.wishbone_types.all;
10 DATA_LINES : positive := 1; -- Number of data lines
11 -- 1=MISO/MOSI, otherwise 2 or 4
12 INPUT_DELAY : natural range 0 to 1 := 1 -- Delay latching of SPI input:
13 -- 0=no delay, 1=clk/2
21 -- SCK = CLK/((CLK_DIV+1)*2) : 0=CLK/2, 1=CLK/4, 2=CLK/6....
23 -- This need to be changed before a command.
24 -- XX TODO add handshake
25 clk_div_i : in natural range 0 to 255;
28 -- Command port (includes write data)
31 -- Valid & ready: command sampled when valid=1 and ready=1
32 cmd_valid_i : in std_ulogic;
33 cmd_ready_o : out std_ulogic;
36 -- 000 : Single bit read+write
37 -- 010 : Single bit read
38 -- 011 : Single bit write
43 cmd_mode_i : in std_ulogic_vector(2 downto 0);
45 -- # clocks-1 in a command (#bits-1)
46 cmd_clks_i : in std_ulogic_vector(2 downto 0);
48 -- Write data (sampled with command)
49 cmd_txd_i : in std_ulogic_vector(7 downto 0);
52 -- Read data port. Data valid when d_ack=1, no ready
53 -- signal, receiver must be ready
55 d_rxd_o : out std_ulogic_vector(7 downto 0);
56 d_ack_o : out std_ulogic := '0';
58 -- Set when all commands are done. Needed for callers to know when
60 bus_idle_o : out std_ulogic;
63 -- SPI port. These might need to go into special IOBUFs or STARTUPE2 on
66 -- Data lines are organized as follow:
70 -- sdat_o(0) is MOSI (master output slave input)
71 -- sdat_i(0) is MISO (master input slave output)
75 -- sdat_o(0..n) are DQ(0..n)
76 -- sdat_i(0..n) are DQ(0..n)
78 -- as such, beware that:
80 -- sdat_o(0) is MOSI (master output slave input)
81 -- sdat_i(1) is MISO (master input slave output)
83 -- In order to leave dealing with the details of how to wire the tristate
84 -- and bidirectional pins to the system specific toplevel, we separate
85 -- the input and output signals, and provide a "sdat_oe" signal which
86 -- is the "output enable" of each line.
89 sdat_o : out std_ulogic_vector(DATA_LINES-1 downto 0);
90 sdat_oe : out std_ulogic_vector(DATA_LINES-1 downto 0);
91 sdat_i : in std_ulogic_vector(DATA_LINES-1 downto 0)
95 architecture rtl of spi_rxtx is
97 -- Internal clock signal. Output is gated by sck_en_int
98 signal sck_0 : std_ulogic;
99 signal sck_1 : std_ulogic;
101 -- Clock divider latch
102 signal clk_div : natural range 0 to 255;
104 -- 1 clk pulses indicating when to send and when to latch
106 -- Typically for CPOL=CPHA
107 -- sck_send is sck falling edge
108 -- sck_recv is sck rising edge
110 -- Those pulses are generated "ahead" of the corresponding
111 -- edge so then are "seen" at the rising sysclk edge matching
112 -- the corresponding sck edgeg.
113 signal sck_send : std_ulogic;
114 signal sck_recv : std_ulogic;
116 -- Command mode latch
117 signal cmd_mode : std_ulogic_vector(2 downto 0);
119 -- Output shift register (use fifo ?)
120 signal oreg : std_ulogic_vector(7 downto 0);
123 signal dat_i_l : std_ulogic_vector(DATA_LINES-1 downto 0);
126 signal dat_ack_l : std_ulogic;
128 -- Delayed recv signal for the read machine
129 signal sck_recv_d : std_ulogic := '0';
131 -- Input shift register (use fifo ?)
132 signal ireg : std_ulogic_vector(7 downto 0) := (others => '0');
135 signal bit_count : std_ulogic_vector(2 downto 0);
137 -- Next/start/stop command signals. Set when counter goes negative
138 signal next_cmd : std_ulogic;
139 signal start_cmd : std_ulogic;
140 signal end_cmd : std_ulogic;
142 function data_single(mode : std_ulogic_vector(2 downto 0)) return boolean is
144 return mode(2) = '0';
146 function data_dual(mode : std_ulogic_vector(2 downto 0)) return boolean is
148 return mode(2 downto 1) = "10";
150 function data_quad(mode : std_ulogic_vector(2 downto 0)) return boolean is
152 return mode(2 downto 1) = "11";
154 function data_write(mode : std_ulogic_vector(2 downto 0)) return boolean is
156 return mode(0) = '1';
159 type state_t is (STANDBY, DATA);
160 signal state : state_t := STANDBY;
163 -- We don't support multiple data lines at this point
164 assert DATA_LINES = 1 or DATA_LINES = 2 or DATA_LINES = 4
165 report "Unsupported DATA_LINES configuration !" severity failure;
169 -- XX HARD WIRE CPOL=1 CPHA=1 for now
170 sck_gen: process(clk)
171 variable counter : integer range 0 to 255;
173 if rising_edge(clk) then
181 elsif counter = clk_div then
185 clk_div <= clk_div_i;
187 -- Internal version of the clock
190 -- Generate send/receive pulses to run out state machine
191 sck_recv <= not sck_0;
194 counter := counter + 1;
199 -- Delayed version of the clock to line up with
200 -- the up/down signals
202 -- XXX Figure out a better way
203 if (state = DATA and end_cmd = '0') or (next_cmd = '1' and cmd_valid_i = '1') then
214 -- Ready to start the next command. This is set on the clock down
215 -- after the counter goes negative.
216 -- Note: in addition to latching a new command, this will cause
217 -- the counter to be reloaded.
218 next_cmd <= '1' when sck_send = '1' and bit_count = "111" else '0';
220 -- We start a command when we have a valid request at that time.
221 start_cmd <= next_cmd and cmd_valid_i;
223 -- We end commands if we get start_cmd and there's nothing to
224 -- start. This sends up to standby holding CLK high
225 end_cmd <= next_cmd and not cmd_valid_i;
227 -- Generate cmd_ready. It will go up and down with sck, we could
228 -- gate it with cmd_valid to make it look cleaner but that would
229 -- add yet another combinational loop on the wishbone that I'm
231 cmd_ready_o <= next_cmd;
233 -- Generate bus_idle_o
234 bus_idle_o <= '1' when state = STANDBY else '0';
236 -- Main state machine. Also generates cmd and data ACKs
237 machine: process(clk)
239 if rising_edge(clk) then
244 -- First clk down of a new cycle. Latch a request if any
246 if start_cmd = '1' then
248 cmd_mode <= cmd_mode_i;
249 elsif end_cmd = '1' then
256 -- Run the bit counter in DATA state. It will update on rising
257 -- SCK edges. It starts at d_clks on command latch
258 count_bit: process(clk)
260 if rising_edge(clk) then
262 bit_count <= (others => '0');
264 if start_cmd = '1' then
265 bit_count <= cmd_clks_i;
266 elsif state /= DATA then
267 bit_count <= (others => '1');
268 elsif sck_recv = '1' then
269 bit_count <= std_ulogic_vector(unsigned(bit_count) - 1);
276 shift_out: process(clk)
278 if rising_edge(clk) then
279 -- Starting a command
280 if start_cmd = '1' then
281 oreg <= cmd_txd_i(7 downto 0);
282 elsif sck_send = '1' then
284 if data_single(cmd_mode) then
285 oreg <= oreg(6 downto 0) & '0';
286 elsif data_dual(cmd_mode) then
287 oreg <= oreg(5 downto 0) & "00";
289 oreg <= oreg(3 downto 0) & "0000";
296 sdat_o(0) <= oreg(7);
297 dl2: if DATA_LINES > 1 generate
298 sdat_o(1) <= oreg(6);
300 dl4: if DATA_LINES > 2 generate
301 sdat_o(2) <= oreg(5);
302 sdat_o(3) <= oreg(4);
305 -- Data lines direction
308 for i in DATA_LINES-1 downto 0 loop
311 -- In single mode, we always enable MOSI, otherwise
312 -- we control the output enable based on the direction
315 if i = 0 and (data_single(cmd_mode) or data_write(cmd_mode)) then
318 if i = 1 and data_dual(cmd_mode) and data_write(cmd_mode) then
321 if i > 0 and data_quad(cmd_mode) and data_write(cmd_mode) then
328 -- Latch input data no delay
329 input_delay_0: if INPUT_DELAY = 0 generate
332 if rising_edge(clk) then
338 -- Latch input data half clock delay
339 input_delay_1: if INPUT_DELAY = 1 generate
342 if falling_edge(clk) then
349 shift_in: process(clk)
351 if rising_edge(clk) then
353 -- Delay the receive signal to match the input latch
355 sck_recv_d <= sck_recv;
360 -- Generate read data acks
361 if bit_count = "000" and sck_recv = '1' then
362 dat_ack_l <= not cmd_mode(0);
367 -- And delay them as well
368 d_ack_o <= dat_ack_l;
370 -- Shift register on delayed data & receive signal
371 if sck_recv_d = '1' then
372 if DATA_LINES = 1 then
373 ireg <= ireg(6 downto 0) & dat_i_l(0);
375 if data_dual(cmd_mode) then
376 ireg <= ireg(5 downto 0) & dat_i_l(1) & dat_i_l(0);
377 elsif data_quad(cmd_mode) then
378 ireg <= ireg(3 downto 0) & dat_i_l(3) & dat_i_l(2) & dat_i_l(1) & dat_i_l(0);
380 assert(data_single(cmd_mode));
381 ireg <= ireg(6 downto 0) & dat_i_l(1);
388 -- Data recieve register