1 from nmigen
import Module
, Signal
, Mux
, Const
2 from nmigen
.hdl
.rec
import Record
, Layout
, DIR_NONE
3 from nmigen
.compat
.sim
import run_simulation
4 from nmigen
.cli
import verilog
, rtlil
5 from nmigen
.compat
.fhdl
.bitcontainer
import value_bits_sign
6 from singlepipe
import flatten
, RecordObject
12 self
.r1
= RecordObject()
13 self
.r1
.sig1
= Signal(32)
14 self
.r1
.r2
= RecordObject()
15 self
.r1
.r2
.sig2
= Signal(32)
16 self
.r1
.r3
= RecordObject()
17 self
.r1
.r3
.sig3
= Signal(32)
18 self
.sig123
= Signal(96)
20 def elaborate(self
, platform
):
24 m
.d
.comb
+= sig1
.eq(self
.r1
.sig1
)
26 m
.d
.comb
+= sig2
.eq(self
.r1
.r2
.sig2
)
28 print (self
.r1
.fields
)
29 print (self
.r1
.shape())
31 m
.d
.comb
+= self
.sig123
.eq(flatten(self
.r1
))
37 yield dut
.r1
.sig1
.eq(5)
38 yield dut
.r1
.r2
.sig2
.eq(10)
40 sig1
= yield dut
.r1
.sig1
42 sig2
= yield dut
.r1
.r2
.sig2
47 ######################################################################
49 ######################################################################
51 if __name__
== '__main__':
54 run_simulation(dut
, testbench(dut
), vcd_name
="test_record1.vcd")
55 vl
= rtlil
.convert(dut
, ports
=[dut
.sig123
, dut
.r1
.sig1
, dut
.r1
.r2
.sig2
])
56 with
open("test_record1.il", "w") as f
: