move RecordObject to singlepipe.py for now

diff --git a/src/add/record_experiment.py b/src/add/record_experiment.py
index 6c2545e09b82524d8bf93a5e42b153798db114bb..6ecd67077d839503111ed2e2d139aaada91f73bd 100644 (file)
--- a/src/add/record_experiment.py
+++ b/src/add/record_experiment.py
@@ -3,22 +3,7 @@ from nmigen.hdl.rec import Record, Layout, DIR_NONE
 from nmigen.compat.sim import run_simulation
 from nmigen.cli import verilog, rtlil
 from nmigen.compat.fhdl.bitcontainer import value_bits_sign
-from singlepipe import flatten
-
-
-class RecordObject(Record):
-    def __init__(self, name=None):
-        Record.__init__(self, layout=[], name=None)
-
-    def __setattr__(self, k, v):
-        if k in dir(Record) or "fields" not in self.__dict__:
-            return object.__setattr__(self, k, v)
-        self.__dict__["fields"][k] = v
-        if isinstance(v, Record):
-            newlayout = {k: (k, v.layout)}
-        else:
-            newlayout = {k: (k, v.shape())}
-        self.__dict__["layout"].fields.update(newlayout)
+from singlepipe import flatten, RecordObject
 
 
 class RecordTest:

diff --git a/src/add/singlepipe.py b/src/add/singlepipe.py
index 085b73dca145f6a24e2be14348007c41db7d96ee..caaedae104501edc47857478ca23fa46fc9206b9 100644 (file)
--- a/src/add/singlepipe.py
+++ b/src/add/singlepipe.py
@@ -174,6 +174,22 @@ from abc import ABCMeta, abstractmethod
 from collections.abc import Sequence
 
 
+class RecordObject(Record):
+    def __init__(self, layout=None, name=None):
+        Record.__init__(self, layout=layout or [], name=None)
+
+    def __setattr__(self, k, v):
+        if k in dir(Record) or "fields" not in self.__dict__:
+            return object.__setattr__(self, k, v)
+        self.__dict__["fields"][k] = v
+        if isinstance(v, Record):
+            newlayout = {k: (k, v.layout)}
+        else:
+            newlayout = {k: (k, v.shape())}
+        self.__dict__["layout"].fields.update(newlayout)
+
+
+
 class PrevControl:
     """ contains signals that come *from* the previous stage (both in and out)
         * i_valid: previous stage indicating all incoming data is valid.