1 """ Pipeline and BufferedHandshake implementation, conforming to the same API.
2 For multi-input and multi-output variants, see multipipe.
4 Associated development bugs:
5 * http://bugs.libre-riscv.org/show_bug.cgi?id=64
6 * http://bugs.libre-riscv.org/show_bug.cgi?id=57
11 a strategically very important function that is identical in function
12 to nmigen's Signal.eq function, except it may take objects, or a list
13 of objects, or a tuple of objects, and where objects may also be
19 stage requires compliance with a strict API that may be
20 implemented in several means, including as a static class.
21 the methods of a stage instance must be as follows:
23 * ispec() - Input data format specification
24 returns an object or a list or tuple of objects, or
25 a Record, each object having an "eq" function which
26 takes responsibility for copying by assignment all
28 * ospec() - Output data format specification
29 requirements as for ospec
30 * process(m, i) - Processes an ispec-formatted object
31 returns a combinatorial block of a result that
32 may be assigned to the output, by way of the "eq"
34 * setup(m, i) - Optional function for setting up submodules
35 may be used for more complex stages, to link
36 the input (i) to submodules. must take responsibility
37 for adding those submodules to the module (m).
38 the submodules must be combinatorial blocks and
39 must have their inputs and output linked combinatorially.
41 Both StageCls (for use with non-static classes) and Stage (for use
42 by static classes) are abstract classes from which, for convenience
43 and as a courtesy to other developers, anything conforming to the
44 Stage API may *choose* to derive.
49 A useful combinatorial wrapper around stages that chains them together
50 and then presents a Stage-API-conformant interface. By presenting
51 the same API as the stages it wraps, it can clearly be used recursively.
56 A convenience class that takes an input shape, output shape, a
57 "processing" function and an optional "setup" function. Honestly
58 though, there's not much more effort to just... create a class
59 that returns a couple of Records (see ExampleAddRecordStage in
65 A convenience class that takes a single function as a parameter,
66 that is chain-called to create the exact same input and output spec.
67 It has a process() function that simply returns its input.
69 Instances of this class are completely redundant if handed to
70 StageChain, however when passed to UnbufferedPipeline they
71 can be used to introduce a single clock delay.
76 The base class for pipelines. Contains previous and next ready/valid/data.
77 Also has an extremely useful "connect" function that can be used to
78 connect a chain of pipelines and present the exact same prev/next
84 A simple stalling clock-synchronised pipeline that has no buffering
85 (unlike BufferedHandshake). Data flows on *every* clock cycle when
86 the conditions are right (this is nominally when the input is valid
87 and the output is ready).
89 A stall anywhere along the line will result in a stall back-propagating
90 down the entire chain. The BufferedHandshake by contrast will buffer
91 incoming data, allowing previous stages one clock cycle's grace before
94 An advantage of the UnbufferedPipeline over the Buffered one is
95 that the amount of logic needed (number of gates) is greatly
96 reduced (no second set of buffers basically)
98 The disadvantage of the UnbufferedPipeline is that the valid/ready
99 logic, if chained together, is *combinatorial*, resulting in
100 progressively larger gate delay.
102 PassThroughHandshake:
105 A Control class that introduces a single clock delay, passing its
106 data through unaltered. Unlike RegisterPipeline (which relies
107 on UnbufferedPipeline and PassThroughStage) it handles ready/valid
113 A convenience class that, because UnbufferedPipeline introduces a single
114 clock delay, when its stage is a PassThroughStage, it results in a Pipeline
115 stage that, duh, delays its (unmodified) input by one clock cycle.
120 nmigen implementation of buffered pipeline stage, based on zipcpu:
121 https://zipcpu.com/blog/2017/08/14/strategies-for-pipelining.html
123 this module requires quite a bit of thought to understand how it works
124 (and why it is needed in the first place). reading the above is
125 *strongly* recommended.
127 unlike john dawson's IEEE754 FPU STB/ACK signalling, which requires
128 the STB / ACK signals to raise and lower (on separate clocks) before
129 data may proceeed (thus only allowing one piece of data to proceed
130 on *ALTERNATE* cycles), the signalling here is a true pipeline
131 where data will flow on *every* clock when the conditions are right.
133 input acceptance conditions are when:
134 * incoming previous-stage strobe (p.i_valid) is HIGH
135 * outgoing previous-stage ready (p.o_ready) is LOW
137 output transmission conditions are when:
138 * outgoing next-stage strobe (n.o_valid) is HIGH
139 * outgoing next-stage ready (n.i_ready) is LOW
141 the tricky bit is when the input has valid data and the output is not
142 ready to accept it. if it wasn't for the clock synchronisation, it
143 would be possible to tell the input "hey don't send that data, we're
144 not ready". unfortunately, it's not possible to "change the past":
145 the previous stage *has no choice* but to pass on its data.
147 therefore, the incoming data *must* be accepted - and stored: that
148 is the responsibility / contract that this stage *must* accept.
149 on the same clock, it's possible to tell the input that it must
150 not send any more data. this is the "stall" condition.
152 we now effectively have *two* possible pieces of data to "choose" from:
153 the buffered data, and the incoming data. the decision as to which
154 to process and output is based on whether we are in "stall" or not.
155 i.e. when the next stage is no longer ready, the output comes from
156 the buffer if a stall had previously occurred, otherwise it comes
157 direct from processing the input.
159 this allows us to respect a synchronous "travelling STB" with what
160 dan calls a "buffered handshake".
162 it's quite a complex state machine!
167 Synchronised pipeline, Based on:
168 https://github.com/ZipCPU/dbgbus/blob/master/hexbus/rtl/hbdeword.v
171 from nmigen
import Signal
, Cat
, Const
, Mux
, Module
, Value
172 from nmigen
.cli
import verilog
, rtlil
173 from nmigen
.lib
.fifo
import SyncFIFO
, SyncFIFOBuffered
174 from nmigen
.hdl
.ast
import ArrayProxy
175 from nmigen
.hdl
.rec
import Record
, Layout
177 from abc
import ABCMeta
, abstractmethod
178 from collections
.abc
import Sequence
179 from queue
import Queue
182 class RecordObject(Record
):
183 def __init__(self
, layout
=None, name
=None):
184 Record
.__init
__(self
, layout
=layout
or [], name
=None)
186 def __setattr__(self
, k
, v
):
188 if (k
.startswith('_') or k
in ["fields", "name", "src_loc"] or
189 k
in dir(Record
) or "fields" not in self
.__dict
__):
190 return object.__setattr
__(self
, k
, v
)
192 #print ("RecordObject setattr", k, v)
193 if isinstance(v
, Record
):
194 newlayout
= {k
: (k
, v
.layout
)}
195 elif isinstance(v
, Value
):
196 newlayout
= {k
: (k
, v
.shape())}
198 newlayout
= {k
: (k
, shape(v
))}
199 self
.layout
.fields
.update(newlayout
)
202 for x
in self
.fields
.values():
210 """ contains signals that come *from* the previous stage (both in and out)
211 * i_valid: previous stage indicating all incoming data is valid.
212 may be a multi-bit signal, where all bits are required
213 to be asserted to indicate "valid".
214 * o_ready: output to next stage indicating readiness to accept data
215 * i_data : an input - added by the user of this class
218 def __init__(self
, i_width
=1, stage_ctl
=False):
219 self
.stage_ctl
= stage_ctl
220 self
.i_valid
= Signal(i_width
, name
="p_i_valid") # prev >>in self
221 self
._o
_ready
= Signal(name
="p_o_ready") # prev <<out self
222 self
.i_data
= None # XXX MUST BE ADDED BY USER
224 self
.s_o_ready
= Signal(name
="p_s_o_rdy") # prev <<out self
225 self
.trigger
= Signal(reset_less
=True)
229 """ public-facing API: indicates (externally) that stage is ready
232 return self
.s_o_ready
# set dynamically by stage
233 return self
._o
_ready
# return this when not under dynamic control
235 def _connect_in(self
, prev
, direct
=False, fn
=None):
236 """ internal helper function to connect stage to an input source.
237 do not use to connect stage-to-stage!
239 i_valid
= prev
.i_valid
if direct
else prev
.i_valid_test
240 i_data
= fn(prev
.i_data
) if fn
is not None else prev
.i_data
241 return [self
.i_valid
.eq(i_valid
),
242 prev
.o_ready
.eq(self
.o_ready
),
243 eq(self
.i_data
, i_data
),
247 def i_valid_test(self
):
248 vlen
= len(self
.i_valid
)
250 # multi-bit case: valid only when i_valid is all 1s
251 all1s
= Const(-1, (len(self
.i_valid
), False))
252 i_valid
= (self
.i_valid
== all1s
)
254 # single-bit i_valid case
255 i_valid
= self
.i_valid
257 # when stage indicates not ready, incoming data
258 # must "appear" to be not ready too
260 i_valid
= i_valid
& self
.s_o_ready
264 def elaborate(self
, platform
):
266 m
.d
.comb
+= self
.trigger
.eq(self
.i_valid_test
& self
.o_ready
)
270 return [self
.i_data
.eq(i
.i_data
),
271 self
.o_ready
.eq(i
.o_ready
),
272 self
.i_valid
.eq(i
.i_valid
)]
277 if hasattr(self
.i_data
, "ports"):
278 yield from self
.i_data
.ports()
279 elif isinstance(self
.i_data
, Sequence
):
280 yield from self
.i_data
289 """ contains the signals that go *to* the next stage (both in and out)
290 * o_valid: output indicating to next stage that data is valid
291 * i_ready: input from next stage indicating that it can accept data
292 * o_data : an output - added by the user of this class
294 def __init__(self
, stage_ctl
=False):
295 self
.stage_ctl
= stage_ctl
296 self
.o_valid
= Signal(name
="n_o_valid") # self out>> next
297 self
.i_ready
= Signal(name
="n_i_ready") # self <<in next
298 self
.o_data
= None # XXX MUST BE ADDED BY USER
300 self
.d_valid
= Signal(reset
=1) # INTERNAL (data valid)
301 self
.trigger
= Signal(reset_less
=True)
304 def i_ready_test(self
):
306 return self
.i_ready
& self
.d_valid
309 def connect_to_next(self
, nxt
):
310 """ helper function to connect to the next stage data/valid/ready.
311 data/valid is passed *TO* nxt, and ready comes *IN* from nxt.
312 use this when connecting stage-to-stage
314 return [nxt
.i_valid
.eq(self
.o_valid
),
315 self
.i_ready
.eq(nxt
.o_ready
),
316 eq(nxt
.i_data
, self
.o_data
),
319 def _connect_out(self
, nxt
, direct
=False, fn
=None):
320 """ internal helper function to connect stage to an output source.
321 do not use to connect stage-to-stage!
323 i_ready
= nxt
.i_ready
if direct
else nxt
.i_ready_test
324 o_data
= fn(nxt
.o_data
) if fn
is not None else nxt
.o_data
325 return [nxt
.o_valid
.eq(self
.o_valid
),
326 self
.i_ready
.eq(i_ready
),
327 eq(o_data
, self
.o_data
),
330 def elaborate(self
, platform
):
332 m
.d
.comb
+= self
.trigger
.eq(self
.i_ready_test
& self
.o_valid
)
338 if hasattr(self
.o_data
, "ports"):
339 yield from self
.o_data
.ports()
340 elif isinstance(self
.o_data
, Sequence
):
341 yield from self
.o_data
350 """ a helper class for iterating twin-argument compound data structures.
352 Record is a special (unusual, recursive) case, where the input may be
353 specified as a dictionary (which may contain further dictionaries,
354 recursively), where the field names of the dictionary must match
355 the Record's field spec. Alternatively, an object with the same
356 member names as the Record may be assigned: it does not have to
359 ArrayProxy is also special-cased, it's a bit messy: whilst ArrayProxy
360 has an eq function, the object being assigned to it (e.g. a python
361 object) might not. despite the *input* having an eq function,
362 that doesn't help us, because it's the *ArrayProxy* that's being
363 assigned to. so.... we cheat. use the ports() function of the
364 python object, enumerate them, find out the list of Signals that way,
367 def iterator2(self
, o
, i
):
368 if isinstance(o
, dict):
369 yield from self
.dict_iter2(o
, i
)
371 if not isinstance(o
, Sequence
):
373 for (ao
, ai
) in zip(o
, i
):
374 #print ("visit", fn, ao, ai)
375 if isinstance(ao
, Record
):
376 yield from self
.record_iter2(ao
, ai
)
377 elif isinstance(ao
, ArrayProxy
) and not isinstance(ai
, Value
):
378 yield from self
.arrayproxy_iter2(ao
, ai
)
382 def dict_iter2(self
, o
, i
):
383 for (k
, v
) in o
.items():
384 print ("d-iter", v
, i
[k
])
388 def _not_quite_working_with_all_unit_tests_record_iter2(self
, ao
, ai
):
389 print ("record_iter2", ao
, ai
, type(ao
), type(ai
))
390 if isinstance(ai
, Value
):
391 if isinstance(ao
, Sequence
):
393 for o
, i
in zip(ao
, ai
):
396 for idx
, (field_name
, field_shape
, _
) in enumerate(ao
.layout
):
397 if isinstance(field_shape
, Layout
):
401 if hasattr(val
, field_name
): # check for attribute
402 val
= getattr(val
, field_name
)
404 val
= val
[field_name
] # dictionary-style specification
405 yield from self
.iterator2(ao
.fields
[field_name
], val
)
407 def record_iter2(self
, ao
, ai
):
408 for idx
, (field_name
, field_shape
, _
) in enumerate(ao
.layout
):
409 if isinstance(field_shape
, Layout
):
413 if hasattr(val
, field_name
): # check for attribute
414 val
= getattr(val
, field_name
)
416 val
= val
[field_name
] # dictionary-style specification
417 yield from self
.iterator2(ao
.fields
[field_name
], val
)
419 def arrayproxy_iter2(self
, ao
, ai
):
421 op
= getattr(ao
, p
.name
)
422 print ("arrayproxy - p", p
, p
.name
)
423 yield from self
.iterator2(op
, p
)
427 """ a helper class for iterating single-argument compound data structures.
430 def iterate(self
, i
):
431 """ iterate a compound structure recursively using yield
433 if not isinstance(i
, Sequence
):
436 #print ("iterate", ai)
437 if isinstance(ai
, Record
):
438 #print ("record", list(ai.layout))
439 yield from self
.record_iter(ai
)
440 elif isinstance(ai
, ArrayProxy
) and not isinstance(ai
, Value
):
441 yield from self
.array_iter(ai
)
445 def record_iter(self
, ai
):
446 for idx
, (field_name
, field_shape
, _
) in enumerate(ai
.layout
):
447 if isinstance(field_shape
, Layout
):
451 if hasattr(val
, field_name
): # check for attribute
452 val
= getattr(val
, field_name
)
454 val
= val
[field_name
] # dictionary-style specification
455 #print ("recidx", idx, field_name, field_shape, val)
456 yield from self
.iterate(val
)
458 def array_iter(self
, ai
):
460 yield from self
.iterate(p
)
464 """ makes signals equal: a helper routine which identifies if it is being
465 passed a list (or tuple) of objects, or signals, or Records, and calls
466 the objects' eq function.
469 for (ao
, ai
) in Visitor2().iterator2(o
, i
):
471 if not isinstance(rres
, Sequence
):
481 #print ("shape?", part)
488 """ flattens a compound structure recursively using Cat
490 from nmigen
.tools
import flatten
491 #res = list(flatten(i)) # works (as of nmigen commit f22106e5) HOWEVER...
492 res
= list(Visitor().iterate(i
)) # needed because input may be a sequence
496 class StageCls(metaclass
=ABCMeta
):
497 """ Class-based "Stage" API. requires instantiation (after derivation)
499 see "Stage API" above.. Note: python does *not* require derivation
500 from this class. All that is required is that the pipelines *have*
501 the functions listed in this class. Derivation from this class
502 is therefore merely a "courtesy" to maintainers.
505 def ispec(self
): pass # REQUIRED
507 def ospec(self
): pass # REQUIRED
509 #def setup(self, m, i): pass # OPTIONAL
511 def process(self
, i
): pass # REQUIRED
514 class Stage(metaclass
=ABCMeta
):
515 """ Static "Stage" API. does not require instantiation (after derivation)
517 see "Stage API" above. Note: python does *not* require derivation
518 from this class. All that is required is that the pipelines *have*
519 the functions listed in this class. Derivation from this class
520 is therefore merely a "courtesy" to maintainers.
532 #def setup(m, i): pass
539 class RecordBasedStage(Stage
):
540 """ convenience class which provides a Records-based layout.
541 honestly it's a lot easier just to create a direct Records-based
542 class (see ExampleAddRecordStage)
544 def __init__(self
, in_shape
, out_shape
, processfn
, setupfn
=None):
545 self
.in_shape
= in_shape
546 self
.out_shape
= out_shape
547 self
.__process
= processfn
548 self
.__setup
= setupfn
549 def ispec(self
): return Record(self
.in_shape
)
550 def ospec(self
): return Record(self
.out_shape
)
551 def process(seif
, i
): return self
.__process
(i
)
552 def setup(seif
, m
, i
): return self
.__setup
(m
, i
)
555 class StageChain(StageCls
):
556 """ pass in a list of stages, and they will automatically be
557 chained together via their input and output specs into a
560 the end result basically conforms to the exact same Stage API.
562 * input to this class will be the input of the first stage
563 * output of first stage goes into input of second
564 * output of second goes into input into third (etc. etc.)
565 * the output of this class will be the output of the last stage
567 def __init__(self
, chain
, specallocate
=False):
569 self
.specallocate
= specallocate
572 return self
.chain
[0].ispec()
575 return self
.chain
[-1].ospec()
577 def _specallocate_setup(self
, m
, i
):
578 for (idx
, c
) in enumerate(self
.chain
):
579 if hasattr(c
, "setup"):
580 c
.setup(m
, i
) # stage may have some module stuff
581 o
= self
.chain
[idx
].ospec() # last assignment survives
582 m
.d
.comb
+= eq(o
, c
.process(i
)) # process input into "o"
583 if idx
== len(self
.chain
)-1:
585 i
= self
.chain
[idx
+1].ispec() # new input on next loop
586 m
.d
.comb
+= eq(i
, o
) # assign to next input
587 return o
# last loop is the output
589 def _noallocate_setup(self
, m
, i
):
590 for (idx
, c
) in enumerate(self
.chain
):
591 if hasattr(c
, "setup"):
592 c
.setup(m
, i
) # stage may have some module stuff
593 i
= o
= c
.process(i
) # store input into "o"
594 return o
# last loop is the output
596 def setup(self
, m
, i
):
597 if self
.specallocate
:
598 self
.o
= self
._specallocate
_setup
(m
, i
)
600 self
.o
= self
._noallocate
_setup
(m
, i
)
602 def process(self
, i
):
603 return self
.o
# conform to Stage API: return last-loop output
607 """ Common functions for Pipeline API
609 def __init__(self
, stage
=None, in_multi
=None, stage_ctl
=False):
610 """ Base class containing ready/valid/data to previous and next stages
612 * p: contains ready/valid to the previous stage
613 * n: contains ready/valid to the next stage
615 Except when calling Controlbase.connect(), user must also:
616 * add i_data member to PrevControl (p) and
617 * add o_data member to NextControl (n)
621 # set up input and output IO ACK (prev/next ready/valid)
622 self
.p
= PrevControl(in_multi
, stage_ctl
)
623 self
.n
= NextControl(stage_ctl
)
625 # set up the input and output data
626 if stage
is not None:
627 self
.p
.i_data
= stage
.ispec() # input type
628 self
.n
.o_data
= stage
.ospec()
630 def connect_to_next(self
, nxt
):
631 """ helper function to connect to the next stage data/valid/ready.
633 return self
.n
.connect_to_next(nxt
.p
)
635 def _connect_in(self
, prev
):
636 """ internal helper function to connect stage to an input source.
637 do not use to connect stage-to-stage!
639 return self
.p
._connect
_in
(prev
.p
)
641 def _connect_out(self
, nxt
):
642 """ internal helper function to connect stage to an output source.
643 do not use to connect stage-to-stage!
645 return self
.n
._connect
_out
(nxt
.n
)
647 def connect(self
, pipechain
):
648 """ connects a chain (list) of Pipeline instances together and
649 links them to this ControlBase instance:
651 in <----> self <---> out
654 [pipe1, pipe2, pipe3, pipe4]
657 out---in out--in out---in
659 Also takes care of allocating i_data/o_data, by looking up
660 the data spec for each end of the pipechain. i.e It is NOT
661 necessary to allocate self.p.i_data or self.n.o_data manually:
662 this is handled AUTOMATICALLY, here.
664 Basically this function is the direct equivalent of StageChain,
665 except that unlike StageChain, the Pipeline logic is followed.
667 Just as StageChain presents an object that conforms to the
668 Stage API from a list of objects that also conform to the
669 Stage API, an object that calls this Pipeline connect function
670 has the exact same pipeline API as the list of pipline objects
673 Thus it becomes possible to build up larger chains recursively.
674 More complex chains (multi-input, multi-output) will have to be
677 eqs
= [] # collated list of assignment statements
679 # connect inter-chain
680 for i
in range(len(pipechain
)-1):
682 pipe2
= pipechain
[i
+1]
683 eqs
+= pipe1
.connect_to_next(pipe2
)
685 # connect front of chain to ourselves
687 self
.p
.i_data
= front
.stage
.ispec()
688 eqs
+= front
._connect
_in
(self
)
690 # connect end of chain to ourselves
692 self
.n
.o_data
= end
.stage
.ospec()
693 eqs
+= end
._connect
_out
(self
)
697 def _postprocess(self
, i
): # XXX DISABLED
698 return i
# RETURNS INPUT
699 if hasattr(self
.stage
, "postprocess"):
700 return self
.stage
.postprocess(i
)
703 def set_input(self
, i
):
704 """ helper function to set the input data
706 return eq(self
.p
.i_data
, i
)
715 def _elaborate(self
, platform
):
716 """ handles case where stage has dynamic ready/valid functions
719 m
.submodules
.p
= self
.p
720 m
.submodules
.n
= self
.n
722 if self
.stage
is not None and hasattr(self
.stage
, "setup"):
723 self
.stage
.setup(m
, self
.p
.i_data
)
725 if not self
.p
.stage_ctl
:
728 # intercept the previous (outgoing) "ready", combine with stage ready
729 m
.d
.comb
+= self
.p
.s_o_ready
.eq(self
.p
._o
_ready
& self
.stage
.d_ready
)
731 # intercept the next (incoming) "ready" and combine it with data valid
732 sdv
= self
.stage
.d_valid(self
.n
.i_ready
)
733 m
.d
.comb
+= self
.n
.d_valid
.eq(self
.n
.i_ready
& sdv
)
738 class BufferedHandshake(ControlBase
):
739 """ buffered pipeline stage. data and strobe signals travel in sync.
740 if ever the input is ready and the output is not, processed data
741 is shunted in a temporary register.
743 Argument: stage. see Stage API above
745 stage-1 p.i_valid >>in stage n.o_valid out>> stage+1
746 stage-1 p.o_ready <<out stage n.i_ready <<in stage+1
747 stage-1 p.i_data >>in stage n.o_data out>> stage+1
753 input data p.i_data is read (only), is processed and goes into an
754 intermediate result store [process()]. this is updated combinatorially.
756 in a non-stall condition, the intermediate result will go into the
757 output (update_output). however if ever there is a stall, it goes
758 into r_data instead [update_buffer()].
760 when the non-stall condition is released, r_data is the first
761 to be transferred to the output [flush_buffer()], and the stall
764 on the next cycle (as long as stall is not raised again) the
765 input may begin to be processed and transferred directly to output.
768 def elaborate(self
, platform
):
769 self
.m
= ControlBase
._elaborate
(self
, platform
)
771 result
= self
.stage
.ospec()
772 r_data
= self
.stage
.ospec()
774 # establish some combinatorial temporaries
775 o_n_validn
= Signal(reset_less
=True)
776 n_i_ready
= Signal(reset_less
=True, name
="n_i_rdy_data")
777 nir_por
= Signal(reset_less
=True)
778 nir_por_n
= Signal(reset_less
=True)
779 p_i_valid
= Signal(reset_less
=True)
780 nir_novn
= Signal(reset_less
=True)
781 nirn_novn
= Signal(reset_less
=True)
782 por_pivn
= Signal(reset_less
=True)
783 npnn
= Signal(reset_less
=True)
784 self
.m
.d
.comb
+= [p_i_valid
.eq(self
.p
.i_valid_test
),
785 o_n_validn
.eq(~self
.n
.o_valid
),
786 n_i_ready
.eq(self
.n
.i_ready_test
),
787 nir_por
.eq(n_i_ready
& self
.p
._o
_ready
),
788 nir_por_n
.eq(n_i_ready
& ~self
.p
._o
_ready
),
789 nir_novn
.eq(n_i_ready | o_n_validn
),
790 nirn_novn
.eq(~n_i_ready
& o_n_validn
),
791 npnn
.eq(nir_por | nirn_novn
),
792 por_pivn
.eq(self
.p
._o
_ready
& ~p_i_valid
)
795 # store result of processing in combinatorial temporary
796 self
.m
.d
.comb
+= eq(result
, self
.stage
.process(self
.p
.i_data
))
798 # if not in stall condition, update the temporary register
799 with self
.m
.If(self
.p
.o_ready
): # not stalled
800 self
.m
.d
.sync
+= eq(r_data
, result
) # update buffer
802 # data pass-through conditions
803 with self
.m
.If(npnn
):
804 o_data
= self
._postprocess
(result
)
805 self
.m
.d
.sync
+= [self
.n
.o_valid
.eq(p_i_valid
), # valid if p_valid
806 eq(self
.n
.o_data
, o_data
), # update output
808 # buffer flush conditions (NOTE: can override data passthru conditions)
809 with self
.m
.If(nir_por_n
): # not stalled
810 # Flush the [already processed] buffer to the output port.
811 o_data
= self
._postprocess
(r_data
)
812 self
.m
.d
.sync
+= [self
.n
.o_valid
.eq(1), # reg empty
813 eq(self
.n
.o_data
, o_data
), # flush buffer
815 # output ready conditions
816 self
.m
.d
.sync
+= self
.p
._o
_ready
.eq(nir_novn | por_pivn
)
821 class SimpleHandshake(ControlBase
):
822 """ simple handshake control. data and strobe signals travel in sync.
823 implements the protocol used by Wishbone and AXI4.
825 Argument: stage. see Stage API above
827 stage-1 p.i_valid >>in stage n.o_valid out>> stage+1
828 stage-1 p.o_ready <<out stage n.i_ready <<in stage+1
829 stage-1 p.i_data >>in stage n.o_data out>> stage+1
834 Inputs Temporary Output Data
835 ------- ---------- ----- ----
836 P P N N PiV& ~NiR& N P
843 0 0 1 0 0 0 0 1 process(i_data)
844 0 0 1 1 0 0 0 1 process(i_data)
848 0 1 1 0 0 0 0 1 process(i_data)
849 0 1 1 1 0 0 0 1 process(i_data)
853 1 0 1 0 0 0 0 1 process(i_data)
854 1 0 1 1 0 0 0 1 process(i_data)
856 1 1 0 0 1 0 1 0 process(i_data)
857 1 1 0 1 1 1 1 0 process(i_data)
858 1 1 1 0 1 0 1 1 process(i_data)
859 1 1 1 1 1 0 1 1 process(i_data)
863 def elaborate(self
, platform
):
864 self
.m
= m
= ControlBase
._elaborate
(self
, platform
)
867 result
= self
.stage
.ospec()
869 # establish some combinatorial temporaries
870 n_i_ready
= Signal(reset_less
=True, name
="n_i_rdy_data")
871 p_i_valid_p_o_ready
= Signal(reset_less
=True)
872 p_i_valid
= Signal(reset_less
=True)
873 m
.d
.comb
+= [p_i_valid
.eq(self
.p
.i_valid_test
),
874 n_i_ready
.eq(self
.n
.i_ready_test
),
875 p_i_valid_p_o_ready
.eq(p_i_valid
& self
.p
.o_ready
),
878 # store result of processing in combinatorial temporary
879 m
.d
.comb
+= eq(result
, self
.stage
.process(self
.p
.i_data
))
881 # previous valid and ready
882 with m
.If(p_i_valid_p_o_ready
):
883 o_data
= self
._postprocess
(result
)
884 m
.d
.sync
+= [r_busy
.eq(1), # output valid
885 eq(self
.n
.o_data
, o_data
), # update output
887 # previous invalid or not ready, however next is accepting
888 with m
.Elif(n_i_ready
):
889 o_data
= self
._postprocess
(result
)
890 m
.d
.sync
+= [eq(self
.n
.o_data
, o_data
)]
891 # TODO: could still send data here (if there was any)
892 #m.d.sync += self.n.o_valid.eq(0) # ...so set output invalid
893 m
.d
.sync
+= r_busy
.eq(0) # ...so set output invalid
895 m
.d
.comb
+= self
.n
.o_valid
.eq(r_busy
)
896 # if next is ready, so is previous
897 m
.d
.comb
+= self
.p
._o
_ready
.eq(n_i_ready
)
902 class UnbufferedPipeline(ControlBase
):
903 """ A simple pipeline stage with single-clock synchronisation
904 and two-way valid/ready synchronised signalling.
906 Note that a stall in one stage will result in the entire pipeline
909 Also that unlike BufferedHandshake, the valid/ready signalling does NOT
910 travel synchronously with the data: the valid/ready signalling
911 combines in a *combinatorial* fashion. Therefore, a long pipeline
912 chain will lengthen propagation delays.
914 Argument: stage. see Stage API, above
916 stage-1 p.i_valid >>in stage n.o_valid out>> stage+1
917 stage-1 p.o_ready <<out stage n.i_ready <<in stage+1
918 stage-1 p.i_data >>in stage n.o_data out>> stage+1
926 p.i_data : StageInput, shaped according to ispec
928 p.o_data : StageOutput, shaped according to ospec
930 r_data : input_shape according to ispec
931 A temporary (buffered) copy of a prior (valid) input.
932 This is HELD if the output is not ready. It is updated
934 result: output_shape according to ospec
935 The output of the combinatorial logic. it is updated
936 COMBINATORIALLY (no clock dependence).
940 Inputs Temp Output Data
962 1 1 0 0 0 1 1 process(i_data)
963 1 1 0 1 1 1 0 process(i_data)
964 1 1 1 0 0 1 1 process(i_data)
965 1 1 1 1 0 1 1 process(i_data)
968 Note: PoR is *NOT* involved in the above decision-making.
971 def elaborate(self
, platform
):
972 self
.m
= m
= ControlBase
._elaborate
(self
, platform
)
974 data_valid
= Signal() # is data valid or not
975 r_data
= self
.stage
.ospec() # output type
978 p_i_valid
= Signal(reset_less
=True)
979 pv
= Signal(reset_less
=True)
980 buf_full
= Signal(reset_less
=True)
981 m
.d
.comb
+= p_i_valid
.eq(self
.p
.i_valid_test
)
982 m
.d
.comb
+= pv
.eq(self
.p
.i_valid
& self
.p
.o_ready
)
983 m
.d
.comb
+= buf_full
.eq(~self
.n
.i_ready_test
& data_valid
)
985 m
.d
.comb
+= self
.n
.o_valid
.eq(data_valid
)
986 m
.d
.comb
+= self
.p
._o
_ready
.eq(~data_valid | self
.n
.i_ready_test
)
987 m
.d
.sync
+= data_valid
.eq(p_i_valid | buf_full
)
990 m
.d
.sync
+= eq(r_data
, self
.stage
.process(self
.p
.i_data
))
991 o_data
= self
._postprocess
(r_data
)
992 m
.d
.comb
+= eq(self
.n
.o_data
, o_data
)
996 class UnbufferedPipeline2(ControlBase
):
997 """ A simple pipeline stage with single-clock synchronisation
998 and two-way valid/ready synchronised signalling.
1000 Note that a stall in one stage will result in the entire pipeline
1003 Also that unlike BufferedHandshake, the valid/ready signalling does NOT
1004 travel synchronously with the data: the valid/ready signalling
1005 combines in a *combinatorial* fashion. Therefore, a long pipeline
1006 chain will lengthen propagation delays.
1008 Argument: stage. see Stage API, above
1010 stage-1 p.i_valid >>in stage n.o_valid out>> stage+1
1011 stage-1 p.o_ready <<out stage n.i_ready <<in stage+1
1012 stage-1 p.i_data >>in stage n.o_data out>> stage+1
1014 +- process-> buf <-+
1017 p.i_data : StageInput, shaped according to ispec
1019 p.o_data : StageOutput, shaped according to ospec
1021 buf : output_shape according to ospec
1022 A temporary (buffered) copy of a valid output
1023 This is HELD if the output is not ready. It is updated
1026 Inputs Temp Output Data
1028 P P N N ~NiR& N P (buf_full)
1033 0 0 0 0 0 0 1 process(i_data)
1034 0 0 0 1 1 1 0 reg (odata, unchanged)
1035 0 0 1 0 0 0 1 process(i_data)
1036 0 0 1 1 0 0 1 process(i_data)
1038 0 1 0 0 0 0 1 process(i_data)
1039 0 1 0 1 1 1 0 reg (odata, unchanged)
1040 0 1 1 0 0 0 1 process(i_data)
1041 0 1 1 1 0 0 1 process(i_data)
1043 1 0 0 0 0 1 1 process(i_data)
1044 1 0 0 1 1 1 0 reg (odata, unchanged)
1045 1 0 1 0 0 1 1 process(i_data)
1046 1 0 1 1 0 1 1 process(i_data)
1048 1 1 0 0 0 1 1 process(i_data)
1049 1 1 0 1 1 1 0 reg (odata, unchanged)
1050 1 1 1 0 0 1 1 process(i_data)
1051 1 1 1 1 0 1 1 process(i_data)
1054 Note: PoR is *NOT* involved in the above decision-making.
1057 def elaborate(self
, platform
):
1058 self
.m
= m
= ControlBase
._elaborate
(self
, platform
)
1060 buf_full
= Signal() # is data valid or not
1061 buf
= self
.stage
.ospec() # output type
1064 p_i_valid
= Signal(reset_less
=True)
1065 m
.d
.comb
+= p_i_valid
.eq(self
.p
.i_valid_test
)
1067 m
.d
.comb
+= self
.n
.o_valid
.eq(buf_full | p_i_valid
)
1068 m
.d
.comb
+= self
.p
._o
_ready
.eq(~buf_full
)
1069 m
.d
.sync
+= buf_full
.eq(~self
.n
.i_ready_test
& self
.n
.o_valid
)
1071 o_data
= Mux(buf_full
, buf
, self
.stage
.process(self
.p
.i_data
))
1072 o_data
= self
._postprocess
(o_data
)
1073 m
.d
.comb
+= eq(self
.n
.o_data
, o_data
)
1074 m
.d
.sync
+= eq(buf
, self
.n
.o_data
)
1079 class PassThroughStage(StageCls
):
1080 """ a pass-through stage which has its input data spec equal to its output,
1081 and "passes through" its data from input to output.
1083 def __init__(self
, iospecfn
):
1084 self
.iospecfn
= iospecfn
1085 def ispec(self
): return self
.iospecfn()
1086 def ospec(self
): return self
.iospecfn()
1087 def process(self
, i
): return i
1090 class PassThroughHandshake(ControlBase
):
1091 """ A control block that delays by one clock cycle.
1093 Inputs Temporary Output Data
1094 ------- ------------------ ----- ----
1095 P P N N PiV& PiV| NiR| pvr N P (pvr)
1096 i o i o PoR ~PoR ~NoV o o
1100 0 0 0 0 0 1 1 0 1 1 odata (unchanged)
1101 0 0 0 1 0 1 0 0 1 0 odata (unchanged)
1102 0 0 1 0 0 1 1 0 1 1 odata (unchanged)
1103 0 0 1 1 0 1 1 0 1 1 odata (unchanged)
1105 0 1 0 0 0 0 1 0 0 1 odata (unchanged)
1106 0 1 0 1 0 0 0 0 0 0 odata (unchanged)
1107 0 1 1 0 0 0 1 0 0 1 odata (unchanged)
1108 0 1 1 1 0 0 1 0 0 1 odata (unchanged)
1110 1 0 0 0 0 1 1 1 1 1 process(in)
1111 1 0 0 1 0 1 0 0 1 0 odata (unchanged)
1112 1 0 1 0 0 1 1 1 1 1 process(in)
1113 1 0 1 1 0 1 1 1 1 1 process(in)
1115 1 1 0 0 1 1 1 1 1 1 process(in)
1116 1 1 0 1 1 1 0 0 1 0 odata (unchanged)
1117 1 1 1 0 1 1 1 1 1 1 process(in)
1118 1 1 1 1 1 1 1 1 1 1 process(in)
1123 def elaborate(self
, platform
):
1124 self
.m
= m
= ControlBase
._elaborate
(self
, platform
)
1126 r_data
= self
.stage
.ospec() # output type
1129 p_i_valid
= Signal(reset_less
=True)
1130 pvr
= Signal(reset_less
=True)
1131 m
.d
.comb
+= p_i_valid
.eq(self
.p
.i_valid_test
)
1132 m
.d
.comb
+= pvr
.eq(p_i_valid
& self
.p
.o_ready
)
1134 m
.d
.comb
+= self
.p
.o_ready
.eq(~self
.n
.o_valid | self
.n
.i_ready_test
)
1135 m
.d
.sync
+= self
.n
.o_valid
.eq(p_i_valid | ~self
.p
.o_ready
)
1137 odata
= Mux(pvr
, self
.stage
.process(self
.p
.i_data
), r_data
)
1138 m
.d
.sync
+= eq(r_data
, odata
)
1139 r_data
= self
._postprocess
(r_data
)
1140 m
.d
.comb
+= eq(self
.n
.o_data
, r_data
)
1145 class RegisterPipeline(UnbufferedPipeline
):
1146 """ A pipeline stage that delays by one clock cycle, creating a
1147 sync'd latch out of o_data and o_valid as an indirect byproduct
1148 of using PassThroughStage
1150 def __init__(self
, iospecfn
):
1151 UnbufferedPipeline
.__init
__(self
, PassThroughStage(iospecfn
))
1154 class FIFOControl(ControlBase
):
1155 """ FIFO Control. Uses SyncFIFO to store data, coincidentally
1156 happens to have same valid/ready signalling as Stage API.
1158 i_data -> fifo.din -> FIFO -> fifo.dout -> o_data
1161 def __init__(self
, depth
, stage
, in_multi
=None, stage_ctl
=False,
1162 fwft
=True, buffered
=False, pipe
=False):
1165 * depth: number of entries in the FIFO
1166 * stage: data processing block
1167 * fwft : first word fall-thru mode (non-fwft introduces delay)
1168 * buffered: use buffered FIFO (introduces extra cycle delay)
1170 NOTE 1: FPGAs may have trouble with the defaults for SyncFIFO
1171 (fwft=True, buffered=False)
1173 NOTE 2: i_data *must* have a shape function. it can therefore
1174 be a Signal, or a Record, or a RecordObject.
1176 data is processed (and located) as follows:
1178 self.p self.stage temp fn temp fn temp fp self.n
1179 i_data->process()->result->cat->din.FIFO.dout->cat(o_data)
1181 yes, really: cat produces a Cat() which can be assigned to.
1182 this is how the FIFO gets de-catted without needing a de-cat
1186 assert not (fwft
and buffered
), "buffered cannot do fwft"
1190 self
.buffered
= buffered
1193 ControlBase
.__init
__(self
, stage
, in_multi
, stage_ctl
)
1195 def elaborate(self
, platform
):
1196 self
.m
= m
= ControlBase
._elaborate
(self
, platform
)
1198 # make a FIFO with a signal of equal width to the o_data.
1199 (fwidth
, _
) = shape(self
.n
.o_data
)
1201 fifo
= SyncFIFOBuffered(fwidth
, self
.fdepth
)
1203 fifo
= Queue(fwidth
, self
.fdepth
, fwft
=self
.fwft
, pipe
=self
.pipe
)
1204 m
.submodules
.fifo
= fifo
1206 # store result of processing in combinatorial temporary
1207 result
= self
.stage
.ospec()
1208 m
.d
.comb
+= eq(result
, self
.stage
.process(self
.p
.i_data
))
1210 # connect previous rdy/valid/data - do cat on i_data
1211 # NOTE: cannot do the PrevControl-looking trick because
1212 # of need to process the data. shaaaame....
1213 m
.d
.comb
+= [fifo
.we
.eq(self
.p
.i_valid_test
),
1214 self
.p
.o_ready
.eq(fifo
.writable
),
1215 eq(fifo
.din
, cat(result
)),
1218 # connect next rdy/valid/data - do cat on o_data
1219 connections
= [self
.n
.o_valid
.eq(fifo
.readable
),
1220 fifo
.re
.eq(self
.n
.i_ready_test
),
1222 if self
.fwft
or self
.buffered
:
1223 m
.d
.comb
+= connections
1225 m
.d
.sync
+= connections
# unbuffered fwft mode needs sync
1226 o_data
= cat(self
.n
.o_data
).eq(fifo
.dout
)
1227 o_data
= self
._postprocess
(o_data
)
1234 class UnbufferedPipeline(FIFOControl
):
1235 def __init__(self
, stage
, in_multi
=None, stage_ctl
=False):
1236 FIFOControl
.__init
__(self
, 1, stage
, in_multi
, stage_ctl
,
1237 fwft
=True, pipe
=False)
1239 # aka "BreakReadyStage" XXX had to set fwft=True to get it to work
1240 class PassThroughHandshake(FIFOControl
):
1241 def __init__(self
, stage
, in_multi
=None, stage_ctl
=False):
1242 FIFOControl
.__init
__(self
, 1, stage
, in_multi
, stage_ctl
,
1243 fwft
=True, pipe
=True)
1245 # this is *probably* BufferedHandshake, although test #997 now succeeds.
1246 class BufferedHandshake(FIFOControl
):
1247 def __init__(self
, stage
, in_multi
=None, stage_ctl
=False):
1248 FIFOControl
.__init
__(self
, 2, stage
, in_multi
, stage_ctl
,
1249 fwft
=True, pipe
=False)
1253 # this is *probably* SimpleHandshake (note: memory cell size=0)
1254 class SimpleHandshake(FIFOControl):
1255 def __init__(self, stage, in_multi=None, stage_ctl=False):
1256 FIFOControl.__init__(self, 0, stage, in_multi, stage_ctl,
1257 fwft=True, pipe=False)