src/add/singlepipe.py

   1 """ Pipeline and BufferedHandshake implementation, conforming to the same API.
   2     For multi-input and multi-output variants, see multipipe.
   3
   4     Associated development bugs:
   5     * http://bugs.libre-riscv.org/show_bug.cgi?id=64
   6     * http://bugs.libre-riscv.org/show_bug.cgi?id=57
   7
   8     eq:
   9     --
  10
  11     a strategically very important function that is identical in function
  12     to nmigen's Signal.eq function, except it may take objects, or a list
  13     of objects, or a tuple of objects, and where objects may also be
  14     Records.
  15
  16     Stage API:
  17     ---------
  18
  19     stage requires compliance with a strict API that may be
  20     implemented in several means, including as a static class.
  21     the methods of a stage instance must be as follows:
  22
  23     * ispec() - Input data format specification
  24                 returns an object or a list or tuple of objects, or
  25                 a Record, each object having an "eq" function which
  26                 takes responsibility for copying by assignment all
  27                 sub-objects
  28     * ospec() - Output data format specification
  29                 requirements as for ospec
  30     * process(m, i) - Processes an ispec-formatted object
  31                 returns a combinatorial block of a result that
  32                 may be assigned to the output, by way of the "eq"
  33                 function
  34     * setup(m, i) - Optional function for setting up submodules
  35                 may be used for more complex stages, to link
  36                 the input (i) to submodules.  must take responsibility
  37                 for adding those submodules to the module (m).
  38                 the submodules must be combinatorial blocks and
  39                 must have their inputs and output linked combinatorially.
  40
  41     Both StageCls (for use with non-static classes) and Stage (for use
  42     by static classes) are abstract classes from which, for convenience
  43     and as a courtesy to other developers, anything conforming to the
  44     Stage API may *choose* to derive.
  45
  46     StageChain:
  47     ----------
  48
  49     A useful combinatorial wrapper around stages that chains them together
  50     and then presents a Stage-API-conformant interface.  By presenting
  51     the same API as the stages it wraps, it can clearly be used recursively.
  52
  53     RecordBasedStage:
  54     ----------------
  55
  56     A convenience class that takes an input shape, output shape, a
  57     "processing" function and an optional "setup" function.  Honestly
  58     though, there's not much more effort to just... create a class
  59     that returns a couple of Records (see ExampleAddRecordStage in
  60     examples).
  61
  62     PassThroughStage:
  63     ----------------
  64
  65     A convenience class that takes a single function as a parameter,
  66     that is chain-called to create the exact same input and output spec.
  67     It has a process() function that simply returns its input.
  68
  69     Instances of this class are completely redundant if handed to
  70     StageChain, however when passed to UnbufferedPipeline they
  71     can be used to introduce a single clock delay.
  72
  73     ControlBase:
  74     -----------
  75
  76     The base class for pipelines.  Contains previous and next ready/valid/data.
  77     Also has an extremely useful "connect" function that can be used to
  78     connect a chain of pipelines and present the exact same prev/next
  79     ready/valid/data API.
  80
  81     UnbufferedPipeline:
  82     ------------------
  83
  84     A simple stalling clock-synchronised pipeline that has no buffering
  85     (unlike BufferedHandshake).  Data flows on *every* clock cycle when
  86     the conditions are right (this is nominally when the input is valid
  87     and the output is ready).
  88
  89     A stall anywhere along the line will result in a stall back-propagating
  90     down the entire chain.  The BufferedHandshake by contrast will buffer
  91     incoming data, allowing previous stages one clock cycle's grace before
  92     also having to stall.
  93
  94     An advantage of the UnbufferedPipeline over the Buffered one is
  95     that the amount of logic needed (number of gates) is greatly
  96     reduced (no second set of buffers basically)
  97
  98     The disadvantage of the UnbufferedPipeline is that the valid/ready
  99     logic, if chained together, is *combinatorial*, resulting in
 100     progressively larger gate delay.
 101
 102     PassThroughHandshake:
 103     ------------------
 104
 105     A Control class that introduces a single clock delay, passing its
 106     data through unaltered.  Unlike RegisterPipeline (which relies
 107     on UnbufferedPipeline and PassThroughStage) it handles ready/valid
 108     itself.
 109
 110     RegisterPipeline:
 111     ----------------
 112
 113     A convenience class that, because UnbufferedPipeline introduces a single
 114     clock delay, when its stage is a PassThroughStage, it results in a Pipeline
 115     stage that, duh, delays its (unmodified) input by one clock cycle.
 116
 117     BufferedHandshake:
 118     ----------------
 119
 120     nmigen implementation of buffered pipeline stage, based on zipcpu:
 121     https://zipcpu.com/blog/2017/08/14/strategies-for-pipelining.html
 122
 123     this module requires quite a bit of thought to understand how it works
 124     (and why it is needed in the first place).  reading the above is
 125     *strongly* recommended.
 126
 127     unlike john dawson's IEEE754 FPU STB/ACK signalling, which requires
 128     the STB / ACK signals to raise and lower (on separate clocks) before
 129     data may proceeed (thus only allowing one piece of data to proceed
 130     on *ALTERNATE* cycles), the signalling here is a true pipeline
 131     where data will flow on *every* clock when the conditions are right.
 132
 133     input acceptance conditions are when:
 134         * incoming previous-stage strobe (p.i_valid) is HIGH
 135         * outgoing previous-stage ready   (p.o_ready) is LOW
 136
 137     output transmission conditions are when:
 138         * outgoing next-stage strobe (n.o_valid) is HIGH
 139         * outgoing next-stage ready   (n.i_ready) is LOW
 140
 141     the tricky bit is when the input has valid data and the output is not
 142     ready to accept it.  if it wasn't for the clock synchronisation, it
 143     would be possible to tell the input "hey don't send that data, we're
 144     not ready".  unfortunately, it's not possible to "change the past":
 145     the previous stage *has no choice* but to pass on its data.
 146
 147     therefore, the incoming data *must* be accepted - and stored: that
 148     is the responsibility / contract that this stage *must* accept.
 149     on the same clock, it's possible to tell the input that it must
 150     not send any more data.  this is the "stall" condition.
 151
 152     we now effectively have *two* possible pieces of data to "choose" from:
 153     the buffered data, and the incoming data.  the decision as to which
 154     to process and output is based on whether we are in "stall" or not.
 155     i.e. when the next stage is no longer ready, the output comes from
 156     the buffer if a stall had previously occurred, otherwise it comes
 157     direct from processing the input.
 158
 159     this allows us to respect a synchronous "travelling STB" with what
 160     dan calls a "buffered handshake".
 161
 162     it's quite a complex state machine!
 163
 164     SimpleHandshake
 165     ---------------
 166
 167     Synchronised pipeline, Based on:
 168     https://github.com/ZipCPU/dbgbus/blob/master/hexbus/rtl/hbdeword.v
 169 """
 170
 171 from nmigen import Signal, Cat, Const, Mux, Module, Value
 172 from nmigen.cli import verilog, rtlil
 173 from nmigen.lib.fifo import SyncFIFO, SyncFIFOBuffered
 174 from nmigen.hdl.ast import ArrayProxy
 175 from nmigen.hdl.rec import Record, Layout
 176
 177 from abc import ABCMeta, abstractmethod
 178 from collections.abc import Sequence
 179 from queue import Queue
 180
 181
 182 class RecordObject(Record):
 183     def __init__(self, layout=None, name=None):
 184         Record.__init__(self, layout=layout or [], name=None)
 185
 186     def __setattr__(self, k, v):
 187         #print (dir(Record))
 188         if (k.startswith('_') or k in ["fields", "name", "src_loc"] or
 189            k in dir(Record) or "fields" not in self.__dict__):
 190             return object.__setattr__(self, k, v)
 191         self.fields[k] = v
 192         #print ("RecordObject setattr", k, v)
 193         if isinstance(v, Record):
 194             newlayout = {k: (k, v.layout)}
 195         elif isinstance(v, Value):
 196             newlayout = {k: (k, v.shape())}
 197         else:
 198             newlayout = {k: (k, shape(v))}
 199         self.layout.fields.update(newlayout)
 200
 201     def __iter__(self):
 202         for x in self.fields.values():
 203             yield x
 204
 205     def ports(self):
 206         return list(self)
 207
 208
 209 class PrevControl:
 210     """ contains signals that come *from* the previous stage (both in and out)
 211         * i_valid: previous stage indicating all incoming data is valid.
 212                    may be a multi-bit signal, where all bits are required
 213                    to be asserted to indicate "valid".
 214         * o_ready: output to next stage indicating readiness to accept data
 215         * i_data : an input - added by the user of this class
 216     """
 217
 218     def __init__(self, i_width=1, stage_ctl=False):
 219         self.stage_ctl = stage_ctl
 220         self.i_valid = Signal(i_width, name="p_i_valid") # prev   >>in  self
 221         self._o_ready = Signal(name="p_o_ready") # prev   <<out self
 222         self.i_data = None # XXX MUST BE ADDED BY USER
 223         if stage_ctl:
 224             self.s_o_ready = Signal(name="p_s_o_rdy") # prev   <<out self
 225         self.trigger = Signal(reset_less=True)
 226
 227     @property
 228     def o_ready(self):
 229         """ public-facing API: indicates (externally) that stage is ready
 230         """
 231         if self.stage_ctl:
 232             return self.s_o_ready # set dynamically by stage
 233         return self._o_ready      # return this when not under dynamic control
 234
 235     def _connect_in(self, prev, direct=False, fn=None):
 236         """ internal helper function to connect stage to an input source.
 237             do not use to connect stage-to-stage!
 238         """
 239         i_valid = prev.i_valid if direct else prev.i_valid_test
 240         i_data = fn(prev.i_data) if fn is not None else prev.i_data
 241         return [self.i_valid.eq(i_valid),
 242                 prev.o_ready.eq(self.o_ready),
 243                 eq(self.i_data, i_data),
 244                ]
 245
 246     @property
 247     def i_valid_test(self):
 248         vlen = len(self.i_valid)
 249         if vlen > 1:
 250             # multi-bit case: valid only when i_valid is all 1s
 251             all1s = Const(-1, (len(self.i_valid), False))
 252             i_valid = (self.i_valid == all1s)
 253         else:
 254             # single-bit i_valid case
 255             i_valid = self.i_valid
 256
 257         # when stage indicates not ready, incoming data
 258         # must "appear" to be not ready too
 259         if self.stage_ctl:
 260             i_valid = i_valid & self.s_o_ready
 261
 262         return i_valid
 263
 264     def elaborate(self, platform):
 265         m = Module()
 266         m.d.comb += self.trigger.eq(self.i_valid_test & self.o_ready)
 267         return m
 268
 269     def eq(self, i):
 270         return [self.i_data.eq(i.i_data),
 271                 self.o_ready.eq(i.o_ready),
 272                 self.i_valid.eq(i.i_valid)]
 273
 274     def __iter__(self):
 275         yield self.i_valid
 276         yield self.o_ready
 277         if hasattr(self.i_data, "ports"):
 278             yield from self.i_data.ports()
 279         elif isinstance(self.i_data, Sequence):
 280             yield from self.i_data
 281         else:
 282             yield self.i_data
 283
 284     def ports(self):
 285         return list(self)
 286
 287
 288 class NextControl:
 289     """ contains the signals that go *to* the next stage (both in and out)
 290         * o_valid: output indicating to next stage that data is valid
 291         * i_ready: input from next stage indicating that it can accept data
 292         * o_data : an output - added by the user of this class
 293     """
 294     def __init__(self, stage_ctl=False):
 295         self.stage_ctl = stage_ctl
 296         self.o_valid = Signal(name="n_o_valid") # self out>>  next
 297         self.i_ready = Signal(name="n_i_ready") # self <<in   next
 298         self.o_data = None # XXX MUST BE ADDED BY USER
 299         #if self.stage_ctl:
 300         self.d_valid = Signal(reset=1) # INTERNAL (data valid)
 301         self.trigger = Signal(reset_less=True)
 302
 303     @property
 304     def i_ready_test(self):
 305         if self.stage_ctl:
 306             return self.i_ready & self.d_valid
 307         return self.i_ready
 308
 309     def connect_to_next(self, nxt):
 310         """ helper function to connect to the next stage data/valid/ready.
 311             data/valid is passed *TO* nxt, and ready comes *IN* from nxt.
 312             use this when connecting stage-to-stage
 313         """
 314         return [nxt.i_valid.eq(self.o_valid),
 315                 self.i_ready.eq(nxt.o_ready),
 316                 eq(nxt.i_data, self.o_data),
 317                ]
 318
 319     def _connect_out(self, nxt, direct=False, fn=None):
 320         """ internal helper function to connect stage to an output source.
 321             do not use to connect stage-to-stage!
 322         """
 323         i_ready = nxt.i_ready if direct else nxt.i_ready_test
 324         o_data = fn(nxt.o_data) if fn is not None else nxt.o_data
 325         return [nxt.o_valid.eq(self.o_valid),
 326                 self.i_ready.eq(i_ready),
 327                 eq(o_data, self.o_data),
 328                ]
 329
 330     def elaborate(self, platform):
 331         m = Module()
 332         m.d.comb += self.trigger.eq(self.i_ready_test & self.o_valid)
 333         return m
 334
 335     def __iter__(self):
 336         yield self.i_ready
 337         yield self.o_valid
 338         if hasattr(self.o_data, "ports"):
 339             yield from self.o_data.ports()
 340         elif isinstance(self.o_data, Sequence):
 341             yield from self.o_data
 342         else:
 343             yield self.o_data
 344
 345     def ports(self):
 346         return list(self)
 347
 348
 349 class Visitor2:
 350     """ a helper class for iterating twin-argument compound data structures.
 351
 352         Record is a special (unusual, recursive) case, where the input may be
 353         specified as a dictionary (which may contain further dictionaries,
 354         recursively), where the field names of the dictionary must match
 355         the Record's field spec.  Alternatively, an object with the same
 356         member names as the Record may be assigned: it does not have to
 357         *be* a Record.
 358
 359         ArrayProxy is also special-cased, it's a bit messy: whilst ArrayProxy
 360         has an eq function, the object being assigned to it (e.g. a python
 361         object) might not.  despite the *input* having an eq function,
 362         that doesn't help us, because it's the *ArrayProxy* that's being
 363         assigned to.  so.... we cheat.  use the ports() function of the
 364         python object, enumerate them, find out the list of Signals that way,
 365         and assign them.
 366     """
 367     def iterator2(self, o, i):
 368         if isinstance(o, dict):
 369             yield from self.dict_iter2(o, i)
 370
 371         if not isinstance(o, Sequence):
 372             o, i = [o], [i]
 373         for (ao, ai) in zip(o, i):
 374             #print ("visit", fn, ao, ai)
 375             if isinstance(ao, Record):
 376                 yield from self.record_iter2(ao, ai)
 377             elif isinstance(ao, ArrayProxy) and not isinstance(ai, Value):
 378                 yield from self.arrayproxy_iter2(ao, ai)
 379             else:
 380                 yield (ao, ai)
 381
 382     def dict_iter2(self, o, i):
 383         for (k, v) in o.items():
 384             print ("d-iter", v, i[k])
 385             yield (v, i[k])
 386         return res
 387
 388     def _not_quite_working_with_all_unit_tests_record_iter2(self, ao, ai):
 389         print ("record_iter2", ao, ai, type(ao), type(ai))
 390         if isinstance(ai, Value):
 391             if isinstance(ao, Sequence):
 392                 ao, ai = [ao], [ai]
 393             for o, i in zip(ao, ai):
 394                 yield (o, i)
 395             return
 396         for idx, (field_name, field_shape, _) in enumerate(ao.layout):
 397             if isinstance(field_shape, Layout):
 398                 val = ai.fields
 399             else:
 400                 val = ai
 401             if hasattr(val, field_name): # check for attribute
 402                 val = getattr(val, field_name)
 403             else:
 404                 val = val[field_name] # dictionary-style specification
 405             yield from self.iterator2(ao.fields[field_name], val)
 406
 407     def record_iter2(self, ao, ai):
 408         for idx, (field_name, field_shape, _) in enumerate(ao.layout):
 409             if isinstance(field_shape, Layout):
 410                 val = ai.fields
 411             else:
 412                 val = ai
 413             if hasattr(val, field_name): # check for attribute
 414                 val = getattr(val, field_name)
 415             else:
 416                 val = val[field_name] # dictionary-style specification
 417             yield from self.iterator2(ao.fields[field_name], val)
 418
 419     def arrayproxy_iter2(self, ao, ai):
 420         for p in ai.ports():
 421             op = getattr(ao, p.name)
 422             print ("arrayproxy - p", p, p.name)
 423             yield from self.iterator2(op, p)
 424
 425
 426 class Visitor:
 427     """ a helper class for iterating single-argument compound data structures.
 428         similar to Visitor2.
 429     """
 430     def iterate(self, i):
 431         """ iterate a compound structure recursively using yield
 432         """
 433         if not isinstance(i, Sequence):
 434             i = [i]
 435         for ai in i:
 436             #print ("iterate", ai)
 437             if isinstance(ai, Record):
 438                 #print ("record", list(ai.layout))
 439                 yield from self.record_iter(ai)
 440             elif isinstance(ai, ArrayProxy) and not isinstance(ai, Value):
 441                 yield from self.array_iter(ai)
 442             else:
 443                 yield ai
 444
 445     def record_iter(self, ai):
 446         for idx, (field_name, field_shape, _) in enumerate(ai.layout):
 447             if isinstance(field_shape, Layout):
 448                 val = ai.fields
 449             else:
 450                 val = ai
 451             if hasattr(val, field_name): # check for attribute
 452                 val = getattr(val, field_name)
 453             else:
 454                 val = val[field_name] # dictionary-style specification
 455             #print ("recidx", idx, field_name, field_shape, val)
 456             yield from self.iterate(val)
 457
 458     def array_iter(self, ai):
 459         for p in ai.ports():
 460             yield from self.iterate(p)
 461
 462
 463 def eq(o, i):
 464     """ makes signals equal: a helper routine which identifies if it is being
 465         passed a list (or tuple) of objects, or signals, or Records, and calls
 466         the objects' eq function.
 467     """
 468     res = []
 469     for (ao, ai) in Visitor2().iterator2(o, i):
 470         rres = ao.eq(ai)
 471         if not isinstance(rres, Sequence):
 472             rres = [rres]
 473         res += rres
 474     return res
 475
 476
 477 def shape(i):
 478     #print ("shape", i)
 479     r = 0
 480     for part in list(i):
 481         #print ("shape?", part)
 482         s, _ = part.shape()
 483         r += s
 484     return r, False
 485
 486
 487 def cat(i):
 488     """ flattens a compound structure recursively using Cat
 489     """
 490     from nmigen.tools import flatten
 491     #res = list(flatten(i)) # works (as of nmigen commit f22106e5) HOWEVER...
 492     res = list(Visitor().iterate(i)) # needed because input may be a sequence
 493     return Cat(*res)
 494
 495
 496 class StageCls(metaclass=ABCMeta):
 497     """ Class-based "Stage" API.  requires instantiation (after derivation)
 498
 499         see "Stage API" above..  Note: python does *not* require derivation
 500         from this class.  All that is required is that the pipelines *have*
 501         the functions listed in this class.  Derivation from this class
 502         is therefore merely a "courtesy" to maintainers.
 503     """
 504     @abstractmethod
 505     def ispec(self): pass       # REQUIRED
 506     @abstractmethod
 507     def ospec(self): pass       # REQUIRED
 508     #@abstractmethod
 509     #def setup(self, m, i): pass # OPTIONAL
 510     @abstractmethod
 511     def process(self, i): pass  # REQUIRED
 512
 513
 514 class Stage(metaclass=ABCMeta):
 515     """ Static "Stage" API.  does not require instantiation (after derivation)
 516
 517         see "Stage API" above.  Note: python does *not* require derivation
 518         from this class.  All that is required is that the pipelines *have*
 519         the functions listed in this class.  Derivation from this class
 520         is therefore merely a "courtesy" to maintainers.
 521     """
 522     @staticmethod
 523     @abstractmethod
 524     def ispec(): pass
 525
 526     @staticmethod
 527     @abstractmethod
 528     def ospec(): pass
 529
 530     #@staticmethod
 531     #@abstractmethod
 532     #def setup(m, i): pass
 533
 534     @staticmethod
 535     @abstractmethod
 536     def process(i): pass
 537
 538
 539 class RecordBasedStage(Stage):
 540     """ convenience class which provides a Records-based layout.
 541         honestly it's a lot easier just to create a direct Records-based
 542         class (see ExampleAddRecordStage)
 543     """
 544     def __init__(self, in_shape, out_shape, processfn, setupfn=None):
 545         self.in_shape = in_shape
 546         self.out_shape = out_shape
 547         self.__process = processfn
 548         self.__setup = setupfn
 549     def ispec(self): return Record(self.in_shape)
 550     def ospec(self): return Record(self.out_shape)
 551     def process(seif, i): return self.__process(i)
 552     def setup(seif, m, i): return self.__setup(m, i)
 553
 554
 555 class StageChain(StageCls):
 556     """ pass in a list of stages, and they will automatically be
 557         chained together via their input and output specs into a
 558         combinatorial chain.
 559
 560         the end result basically conforms to the exact same Stage API.
 561
 562         * input to this class will be the input of the first stage
 563         * output of first stage goes into input of second
 564         * output of second goes into input into third (etc. etc.)
 565         * the output of this class will be the output of the last stage
 566     """
 567     def __init__(self, chain, specallocate=False):
 568         self.chain = chain
 569         self.specallocate = specallocate
 570
 571     def ispec(self):
 572         return self.chain[0].ispec()
 573
 574     def ospec(self):
 575         return self.chain[-1].ospec()
 576
 577     def _specallocate_setup(self, m, i):
 578         for (idx, c) in enumerate(self.chain):
 579             if hasattr(c, "setup"):
 580                 c.setup(m, i)               # stage may have some module stuff
 581             o = self.chain[idx].ospec()     # last assignment survives
 582             m.d.comb += eq(o, c.process(i)) # process input into "o"
 583             if idx == len(self.chain)-1:
 584                 break
 585             i = self.chain[idx+1].ispec()   # new input on next loop
 586             m.d.comb += eq(i, o)            # assign to next input
 587         return o                            # last loop is the output
 588
 589     def _noallocate_setup(self, m, i):
 590         for (idx, c) in enumerate(self.chain):
 591             if hasattr(c, "setup"):
 592                 c.setup(m, i)               # stage may have some module stuff
 593             i = o = c.process(i)            # store input into "o"
 594         return o                            # last loop is the output
 595
 596     def setup(self, m, i):
 597         if self.specallocate:
 598             self.o = self._specallocate_setup(m, i)
 599         else:
 600             self.o = self._noallocate_setup(m, i)
 601
 602     def process(self, i):
 603         return self.o # conform to Stage API: return last-loop output
 604
 605
 606 class ControlBase:
 607     """ Common functions for Pipeline API
 608     """
 609     def __init__(self, stage=None, in_multi=None, stage_ctl=False):
 610         """ Base class containing ready/valid/data to previous and next stages
 611
 612             * p: contains ready/valid to the previous stage
 613             * n: contains ready/valid to the next stage
 614
 615             Except when calling Controlbase.connect(), user must also:
 616             * add i_data member to PrevControl (p) and
 617             * add o_data member to NextControl (n)
 618         """
 619         self.stage = stage
 620
 621         # set up input and output IO ACK (prev/next ready/valid)
 622         self.p = PrevControl(in_multi, stage_ctl)
 623         self.n = NextControl(stage_ctl)
 624
 625         # set up the input and output data
 626         if stage is not None:
 627             self.p.i_data = stage.ispec() # input type
 628             self.n.o_data = stage.ospec()
 629
 630     def connect_to_next(self, nxt):
 631         """ helper function to connect to the next stage data/valid/ready.
 632         """
 633         return self.n.connect_to_next(nxt.p)
 634
 635     def _connect_in(self, prev):
 636         """ internal helper function to connect stage to an input source.
 637             do not use to connect stage-to-stage!
 638         """
 639         return self.p._connect_in(prev.p)
 640
 641     def _connect_out(self, nxt):
 642         """ internal helper function to connect stage to an output source.
 643             do not use to connect stage-to-stage!
 644         """
 645         return self.n._connect_out(nxt.n)
 646
 647     def connect(self, pipechain):
 648         """ connects a chain (list) of Pipeline instances together and
 649             links them to this ControlBase instance:
 650
 651                       in <----> self <---> out
 652                        |                   ^
 653                        v                   |
 654                     [pipe1, pipe2, pipe3, pipe4]
 655                        |    ^  |    ^  |     ^
 656                        v    |  v    |  v     |
 657                      out---in out--in out---in
 658
 659             Also takes care of allocating i_data/o_data, by looking up
 660             the data spec for each end of the pipechain.  i.e It is NOT
 661             necessary to allocate self.p.i_data or self.n.o_data manually:
 662             this is handled AUTOMATICALLY, here.
 663
 664             Basically this function is the direct equivalent of StageChain,
 665             except that unlike StageChain, the Pipeline logic is followed.
 666
 667             Just as StageChain presents an object that conforms to the
 668             Stage API from a list of objects that also conform to the
 669             Stage API, an object that calls this Pipeline connect function
 670             has the exact same pipeline API as the list of pipline objects
 671             it is called with.
 672
 673             Thus it becomes possible to build up larger chains recursively.
 674             More complex chains (multi-input, multi-output) will have to be
 675             done manually.
 676         """
 677         eqs = [] # collated list of assignment statements
 678
 679         # connect inter-chain
 680         for i in range(len(pipechain)-1):
 681             pipe1 = pipechain[i]
 682             pipe2 = pipechain[i+1]
 683             eqs += pipe1.connect_to_next(pipe2)
 684
 685         # connect front of chain to ourselves
 686         front = pipechain[0]
 687         self.p.i_data = front.stage.ispec()
 688         eqs += front._connect_in(self)
 689
 690         # connect end of chain to ourselves
 691         end = pipechain[-1]
 692         self.n.o_data = end.stage.ospec()
 693         eqs += end._connect_out(self)
 694
 695         return eqs
 696
 697     def _postprocess(self, i): # XXX DISABLED
 698         return i # RETURNS INPUT
 699         if hasattr(self.stage, "postprocess"):
 700             return self.stage.postprocess(i)
 701         return i
 702
 703     def set_input(self, i):
 704         """ helper function to set the input data
 705         """
 706         return eq(self.p.i_data, i)
 707
 708     def __iter__(self):
 709         yield from self.p
 710         yield from self.n
 711
 712     def ports(self):
 713         return list(self)
 714
 715     def _elaborate(self, platform):
 716         """ handles case where stage has dynamic ready/valid functions
 717         """
 718         m = Module()
 719         m.submodules.p = self.p
 720         m.submodules.n = self.n
 721
 722         if self.stage is not None and hasattr(self.stage, "setup"):
 723             self.stage.setup(m, self.p.i_data)
 724
 725         if not self.p.stage_ctl:
 726             return m
 727
 728         # intercept the previous (outgoing) "ready", combine with stage ready
 729         m.d.comb += self.p.s_o_ready.eq(self.p._o_ready & self.stage.d_ready)
 730
 731         # intercept the next (incoming) "ready" and combine it with data valid
 732         sdv = self.stage.d_valid(self.n.i_ready)
 733         m.d.comb += self.n.d_valid.eq(self.n.i_ready & sdv)
 734
 735         return m
 736
 737
 738 class BufferedHandshake(ControlBase):
 739     """ buffered pipeline stage.  data and strobe signals travel in sync.
 740         if ever the input is ready and the output is not, processed data
 741         is shunted in a temporary register.
 742
 743         Argument: stage.  see Stage API above
 744
 745         stage-1   p.i_valid >>in   stage   n.o_valid out>>   stage+1
 746         stage-1   p.o_ready <<out  stage   n.i_ready <<in    stage+1
 747         stage-1   p.i_data  >>in   stage   n.o_data  out>>   stage+1
 748                               |             |
 749                             process --->----^
 750                               |             |
 751                               +-- r_data ->-+
 752
 753         input data p.i_data is read (only), is processed and goes into an
 754         intermediate result store [process()].  this is updated combinatorially.
 755
 756         in a non-stall condition, the intermediate result will go into the
 757         output (update_output).  however if ever there is a stall, it goes
 758         into r_data instead [update_buffer()].
 759
 760         when the non-stall condition is released, r_data is the first
 761         to be transferred to the output [flush_buffer()], and the stall
 762         condition cleared.
 763
 764         on the next cycle (as long as stall is not raised again) the
 765         input may begin to be processed and transferred directly to output.
 766     """
 767
 768     def elaborate(self, platform):
 769         self.m = ControlBase._elaborate(self, platform)
 770
 771         result = self.stage.ospec()
 772         r_data = self.stage.ospec()
 773
 774         # establish some combinatorial temporaries
 775         o_n_validn = Signal(reset_less=True)
 776         n_i_ready = Signal(reset_less=True, name="n_i_rdy_data")
 777         nir_por = Signal(reset_less=True)
 778         nir_por_n = Signal(reset_less=True)
 779         p_i_valid = Signal(reset_less=True)
 780         nir_novn = Signal(reset_less=True)
 781         nirn_novn = Signal(reset_less=True)
 782         por_pivn = Signal(reset_less=True)
 783         npnn = Signal(reset_less=True)
 784         self.m.d.comb += [p_i_valid.eq(self.p.i_valid_test),
 785                      o_n_validn.eq(~self.n.o_valid),
 786                      n_i_ready.eq(self.n.i_ready_test),
 787                      nir_por.eq(n_i_ready & self.p._o_ready),
 788                      nir_por_n.eq(n_i_ready & ~self.p._o_ready),
 789                      nir_novn.eq(n_i_ready | o_n_validn),
 790                      nirn_novn.eq(~n_i_ready & o_n_validn),
 791                      npnn.eq(nir_por | nirn_novn),
 792                      por_pivn.eq(self.p._o_ready & ~p_i_valid)
 793         ]
 794
 795         # store result of processing in combinatorial temporary
 796         self.m.d.comb += eq(result, self.stage.process(self.p.i_data))
 797
 798         # if not in stall condition, update the temporary register
 799         with self.m.If(self.p.o_ready): # not stalled
 800             self.m.d.sync += eq(r_data, result) # update buffer
 801
 802         # data pass-through conditions
 803         with self.m.If(npnn):
 804             o_data = self._postprocess(result)
 805             self.m.d.sync += [self.n.o_valid.eq(p_i_valid), # valid if p_valid
 806                               eq(self.n.o_data, o_data),    # update output
 807                              ]
 808         # buffer flush conditions (NOTE: can override data passthru conditions)
 809         with self.m.If(nir_por_n): # not stalled
 810             # Flush the [already processed] buffer to the output port.
 811             o_data = self._postprocess(r_data)
 812             self.m.d.sync += [self.n.o_valid.eq(1),  # reg empty
 813                               eq(self.n.o_data, o_data), # flush buffer
 814                              ]
 815         # output ready conditions
 816         self.m.d.sync += self.p._o_ready.eq(nir_novn | por_pivn)
 817
 818         return self.m
 819
 820
 821 class SimpleHandshake(ControlBase):
 822     """ simple handshake control.  data and strobe signals travel in sync.
 823         implements the protocol used by Wishbone and AXI4.
 824
 825         Argument: stage.  see Stage API above
 826
 827         stage-1   p.i_valid >>in   stage   n.o_valid out>>   stage+1
 828         stage-1   p.o_ready <<out  stage   n.i_ready <<in    stage+1
 829         stage-1   p.i_data  >>in   stage   n.o_data  out>>   stage+1
 830                               |             |
 831                               +--process->--^
 832         Truth Table
 833
 834         Inputs   Temporary  Output Data
 835         -------  ---------- -----  ----
 836         P P N N  PiV& ~NiR&  N P
 837         i o i o  PoR  NoV    o o
 838         V R R V              V R
 839
 840         -------   -    -     - -
 841         0 0 0 0   0    0    >0 0    reg
 842         0 0 0 1   0    1    >1 0    reg
 843         0 0 1 0   0    0     0 1    process(i_data)
 844         0 0 1 1   0    0     0 1    process(i_data)
 845         -------   -    -     - -
 846         0 1 0 0   0    0    >0 0    reg
 847         0 1 0 1   0    1    >1 0    reg
 848         0 1 1 0   0    0     0 1    process(i_data)
 849         0 1 1 1   0    0     0 1    process(i_data)
 850         -------   -    -     - -
 851         1 0 0 0   0    0    >0 0    reg
 852         1 0 0 1   0    1    >1 0    reg
 853         1 0 1 0   0    0     0 1    process(i_data)
 854         1 0 1 1   0    0     0 1    process(i_data)
 855         -------   -    -     - -
 856         1 1 0 0   1    0     1 0    process(i_data)
 857         1 1 0 1   1    1     1 0    process(i_data)
 858         1 1 1 0   1    0     1 1    process(i_data)
 859         1 1 1 1   1    0     1 1    process(i_data)
 860         -------   -    -     - -
 861     """
 862
 863     def elaborate(self, platform):
 864         self.m = m = ControlBase._elaborate(self, platform)
 865
 866         r_busy = Signal()
 867         result = self.stage.ospec()
 868
 869         # establish some combinatorial temporaries
 870         n_i_ready = Signal(reset_less=True, name="n_i_rdy_data")
 871         p_i_valid_p_o_ready = Signal(reset_less=True)
 872         p_i_valid = Signal(reset_less=True)
 873         m.d.comb += [p_i_valid.eq(self.p.i_valid_test),
 874                      n_i_ready.eq(self.n.i_ready_test),
 875                      p_i_valid_p_o_ready.eq(p_i_valid & self.p.o_ready),
 876         ]
 877
 878         # store result of processing in combinatorial temporary
 879         m.d.comb += eq(result, self.stage.process(self.p.i_data))
 880
 881         # previous valid and ready
 882         with m.If(p_i_valid_p_o_ready):
 883             o_data = self._postprocess(result)
 884             m.d.sync += [r_busy.eq(1),      # output valid
 885                          eq(self.n.o_data, o_data), # update output
 886                         ]
 887         # previous invalid or not ready, however next is accepting
 888         with m.Elif(n_i_ready):
 889             o_data = self._postprocess(result)
 890             m.d.sync += [eq(self.n.o_data, o_data)]
 891             # TODO: could still send data here (if there was any)
 892             #m.d.sync += self.n.o_valid.eq(0) # ...so set output invalid
 893             m.d.sync += r_busy.eq(0) # ...so set output invalid
 894
 895         m.d.comb += self.n.o_valid.eq(r_busy)
 896         # if next is ready, so is previous
 897         m.d.comb += self.p._o_ready.eq(n_i_ready)
 898
 899         return self.m
 900
 901
 902 class UnbufferedPipeline(ControlBase):
 903     """ A simple pipeline stage with single-clock synchronisation
 904         and two-way valid/ready synchronised signalling.
 905
 906         Note that a stall in one stage will result in the entire pipeline
 907         chain stalling.
 908
 909         Also that unlike BufferedHandshake, the valid/ready signalling does NOT
 910         travel synchronously with the data: the valid/ready signalling
 911         combines in a *combinatorial* fashion.  Therefore, a long pipeline
 912         chain will lengthen propagation delays.
 913
 914         Argument: stage.  see Stage API, above
 915
 916         stage-1   p.i_valid >>in   stage   n.o_valid out>>   stage+1
 917         stage-1   p.o_ready <<out  stage   n.i_ready <<in    stage+1
 918         stage-1   p.i_data  >>in   stage   n.o_data  out>>   stage+1
 919                               |             |
 920                             r_data        result
 921                               |             |
 922                               +--process ->-+
 923
 924         Attributes:
 925         -----------
 926         p.i_data : StageInput, shaped according to ispec
 927             The pipeline input
 928         p.o_data : StageOutput, shaped according to ospec
 929             The pipeline output
 930         r_data : input_shape according to ispec
 931             A temporary (buffered) copy of a prior (valid) input.
 932             This is HELD if the output is not ready.  It is updated
 933             SYNCHRONOUSLY.
 934         result: output_shape according to ospec
 935             The output of the combinatorial logic.  it is updated
 936             COMBINATORIALLY (no clock dependence).
 937
 938         Truth Table
 939
 940         Inputs  Temp  Output  Data
 941         -------   -   -----   ----
 942         P P N N ~NiR&  N P
 943         i o i o  NoV   o o
 944         V R R V        V R
 945
 946         -------   -    - -
 947         0 0 0 0   0    0 1    reg
 948         0 0 0 1   1    1 0    reg
 949         0 0 1 0   0    0 1    reg
 950         0 0 1 1   0    0 1    reg
 951         -------   -    - -
 952         0 1 0 0   0    0 1    reg
 953         0 1 0 1   1    1 0    reg
 954         0 1 1 0   0    0 1    reg
 955         0 1 1 1   0    0 1    reg
 956         -------   -    - -
 957         1 0 0 0   0    1 1    reg
 958         1 0 0 1   1    1 0    reg
 959         1 0 1 0   0    1 1    reg
 960         1 0 1 1   0    1 1    reg
 961         -------   -    - -
 962         1 1 0 0   0    1 1    process(i_data)
 963         1 1 0 1   1    1 0    process(i_data)
 964         1 1 1 0   0    1 1    process(i_data)
 965         1 1 1 1   0    1 1    process(i_data)
 966         -------   -    - -
 967
 968         Note: PoR is *NOT* involved in the above decision-making.
 969     """
 970
 971     def elaborate(self, platform):
 972         self.m = m = ControlBase._elaborate(self, platform)
 973
 974         data_valid = Signal() # is data valid or not
 975         r_data = self.stage.ospec() # output type
 976
 977         # some temporaries
 978         p_i_valid = Signal(reset_less=True)
 979         pv = Signal(reset_less=True)
 980         buf_full = Signal(reset_less=True)
 981         m.d.comb += p_i_valid.eq(self.p.i_valid_test)
 982         m.d.comb += pv.eq(self.p.i_valid & self.p.o_ready)
 983         m.d.comb += buf_full.eq(~self.n.i_ready_test & data_valid)
 984
 985         m.d.comb += self.n.o_valid.eq(data_valid)
 986         m.d.comb += self.p._o_ready.eq(~data_valid | self.n.i_ready_test)
 987         m.d.sync += data_valid.eq(p_i_valid | buf_full)
 988
 989         with m.If(pv):
 990             m.d.sync += eq(r_data, self.stage.process(self.p.i_data))
 991         o_data = self._postprocess(r_data)
 992         m.d.comb += eq(self.n.o_data, o_data)
 993
 994         return self.m
 995
 996 class UnbufferedPipeline2(ControlBase):
 997     """ A simple pipeline stage with single-clock synchronisation
 998         and two-way valid/ready synchronised signalling.
 999
1000         Note that a stall in one stage will result in the entire pipeline
1001         chain stalling.
1002
1003         Also that unlike BufferedHandshake, the valid/ready signalling does NOT
1004         travel synchronously with the data: the valid/ready signalling
1005         combines in a *combinatorial* fashion.  Therefore, a long pipeline
1006         chain will lengthen propagation delays.
1007
1008         Argument: stage.  see Stage API, above
1009
1010         stage-1   p.i_valid >>in   stage   n.o_valid out>>   stage+1
1011         stage-1   p.o_ready <<out  stage   n.i_ready <<in    stage+1
1012         stage-1   p.i_data  >>in   stage   n.o_data  out>>   stage+1
1013                               |             |    |
1014                               +- process-> buf <-+
1015         Attributes:
1016         -----------
1017         p.i_data : StageInput, shaped according to ispec
1018             The pipeline input
1019         p.o_data : StageOutput, shaped according to ospec
1020             The pipeline output
1021         buf : output_shape according to ospec
1022             A temporary (buffered) copy of a valid output
1023             This is HELD if the output is not ready.  It is updated
1024             SYNCHRONOUSLY.
1025
1026         Inputs  Temp  Output Data
1027         -------   -   -----
1028         P P N N ~NiR&  N P   (buf_full)
1029         i o i o  NoV   o o
1030         V R R V        V R
1031
1032         -------   -    - -
1033         0 0 0 0   0    0 1   process(i_data)
1034         0 0 0 1   1    1 0   reg (odata, unchanged)
1035         0 0 1 0   0    0 1   process(i_data)
1036         0 0 1 1   0    0 1   process(i_data)
1037         -------   -    - -
1038         0 1 0 0   0    0 1   process(i_data)
1039         0 1 0 1   1    1 0   reg (odata, unchanged)
1040         0 1 1 0   0    0 1   process(i_data)
1041         0 1 1 1   0    0 1   process(i_data)
1042         -------   -    - -
1043         1 0 0 0   0    1 1   process(i_data)
1044         1 0 0 1   1    1 0   reg (odata, unchanged)
1045         1 0 1 0   0    1 1   process(i_data)
1046         1 0 1 1   0    1 1   process(i_data)
1047         -------   -    - -
1048         1 1 0 0   0    1 1   process(i_data)
1049         1 1 0 1   1    1 0   reg (odata, unchanged)
1050         1 1 1 0   0    1 1   process(i_data)
1051         1 1 1 1   0    1 1   process(i_data)
1052         -------   -    - -
1053
1054         Note: PoR is *NOT* involved in the above decision-making.
1055     """
1056
1057     def elaborate(self, platform):
1058         self.m = m = ControlBase._elaborate(self, platform)
1059
1060         buf_full = Signal() # is data valid or not
1061         buf = self.stage.ospec() # output type
1062
1063         # some temporaries
1064         p_i_valid = Signal(reset_less=True)
1065         m.d.comb += p_i_valid.eq(self.p.i_valid_test)
1066
1067         m.d.comb += self.n.o_valid.eq(buf_full | p_i_valid)
1068         m.d.comb += self.p._o_ready.eq(~buf_full)
1069         m.d.sync += buf_full.eq(~self.n.i_ready_test & self.n.o_valid)
1070
1071         o_data = Mux(buf_full, buf, self.stage.process(self.p.i_data))
1072         o_data = self._postprocess(o_data)
1073         m.d.comb += eq(self.n.o_data, o_data)
1074         m.d.sync += eq(buf, self.n.o_data)
1075
1076         return self.m
1077
1078
1079 class PassThroughStage(StageCls):
1080     """ a pass-through stage which has its input data spec equal to its output,
1081         and "passes through" its data from input to output.
1082     """
1083     def __init__(self, iospecfn):
1084         self.iospecfn = iospecfn
1085     def ispec(self): return self.iospecfn()
1086     def ospec(self): return self.iospecfn()
1087     def process(self, i): return i
1088
1089
1090 class PassThroughHandshake(ControlBase):
1091     """ A control block that delays by one clock cycle.
1092
1093         Inputs   Temporary          Output Data
1094         -------  ------------------  ----- ----
1095         P P N N  PiV& PiV| NiR| pvr   N P  (pvr)
1096         i o i o  PoR  ~PoR ~NoV       o o
1097         V R R V                       V R
1098
1099         -------   -    -    -   -     - -
1100         0 0 0 0   0    1    1   0     1 1   odata (unchanged)
1101         0 0 0 1   0    1    0   0     1 0   odata (unchanged)
1102         0 0 1 0   0    1    1   0     1 1   odata (unchanged)
1103         0 0 1 1   0    1    1   0     1 1   odata (unchanged)
1104         -------   -    -    -   -     - -
1105         0 1 0 0   0    0    1   0     0 1   odata (unchanged)
1106         0 1 0 1   0    0    0   0     0 0   odata (unchanged)
1107         0 1 1 0   0    0    1   0     0 1   odata (unchanged)
1108         0 1 1 1   0    0    1   0     0 1   odata (unchanged)
1109         -------   -    -    -   -     - -
1110         1 0 0 0   0    1    1   1     1 1   process(in)
1111         1 0 0 1   0    1    0   0     1 0   odata (unchanged)
1112         1 0 1 0   0    1    1   1     1 1   process(in)
1113         1 0 1 1   0    1    1   1     1 1   process(in)
1114         -------   -    -    -   -     - -
1115         1 1 0 0   1    1    1   1     1 1   process(in)
1116         1 1 0 1   1    1    0   0     1 0   odata (unchanged)
1117         1 1 1 0   1    1    1   1     1 1   process(in)
1118         1 1 1 1   1    1    1   1     1 1   process(in)
1119         -------   -    -    -   -     - -
1120
1121     """
1122
1123     def elaborate(self, platform):
1124         self.m = m = ControlBase._elaborate(self, platform)
1125
1126         r_data = self.stage.ospec() # output type
1127
1128         # temporaries
1129         p_i_valid = Signal(reset_less=True)
1130         pvr = Signal(reset_less=True)
1131         m.d.comb += p_i_valid.eq(self.p.i_valid_test)
1132         m.d.comb += pvr.eq(p_i_valid & self.p.o_ready)
1133
1134         m.d.comb += self.p.o_ready.eq(~self.n.o_valid |  self.n.i_ready_test)
1135         m.d.sync += self.n.o_valid.eq(p_i_valid       | ~self.p.o_ready)
1136
1137         odata = Mux(pvr, self.stage.process(self.p.i_data), r_data)
1138         m.d.sync += eq(r_data, odata)
1139         r_data = self._postprocess(r_data)
1140         m.d.comb += eq(self.n.o_data, r_data)
1141
1142         return m
1143
1144
1145 class RegisterPipeline(UnbufferedPipeline):
1146     """ A pipeline stage that delays by one clock cycle, creating a
1147         sync'd latch out of o_data and o_valid as an indirect byproduct
1148         of using PassThroughStage
1149     """
1150     def __init__(self, iospecfn):
1151         UnbufferedPipeline.__init__(self, PassThroughStage(iospecfn))
1152
1153
1154 class FIFOControl(ControlBase):
1155     """ FIFO Control.  Uses SyncFIFO to store data, coincidentally
1156         happens to have same valid/ready signalling as Stage API.
1157
1158         i_data -> fifo.din -> FIFO -> fifo.dout -> o_data
1159     """
1160
1161     def __init__(self, depth, stage, in_multi=None, stage_ctl=False,
1162                                      fwft=True, buffered=False, pipe=False):
1163         """ FIFO Control
1164
1165             * depth: number of entries in the FIFO
1166             * stage: data processing block
1167             * fwft : first word fall-thru mode (non-fwft introduces delay)
1168             * buffered: use buffered FIFO (introduces extra cycle delay)
1169
1170             NOTE 1: FPGAs may have trouble with the defaults for SyncFIFO
1171                     (fwft=True, buffered=False)
1172
1173             NOTE 2: i_data *must* have a shape function.  it can therefore
1174                     be a Signal, or a Record, or a RecordObject.
1175
1176             data is processed (and located) as follows:
1177
1178             self.p  self.stage temp    fn temp  fn  temp  fp   self.n
1179             i_data->process()->result->cat->din.FIFO.dout->cat(o_data)
1180
1181             yes, really: cat produces a Cat() which can be assigned to.
1182             this is how the FIFO gets de-catted without needing a de-cat
1183             function
1184         """
1185
1186         assert not (fwft and buffered), "buffered cannot do fwft"
1187         if buffered:
1188             depth += 1
1189         self.fwft = fwft
1190         self.buffered = buffered
1191         self.pipe = pipe
1192         self.fdepth = depth
1193         ControlBase.__init__(self, stage, in_multi, stage_ctl)
1194
1195     def elaborate(self, platform):
1196         self.m = m = ControlBase._elaborate(self, platform)
1197
1198         # make a FIFO with a signal of equal width to the o_data.
1199         (fwidth, _) = shape(self.n.o_data)
1200         if self.buffered:
1201             fifo = SyncFIFOBuffered(fwidth, self.fdepth)
1202         else:
1203             fifo = Queue(fwidth, self.fdepth, fwft=self.fwft, pipe=self.pipe)
1204         m.submodules.fifo = fifo
1205
1206         # store result of processing in combinatorial temporary
1207         result = self.stage.ospec()
1208         m.d.comb += eq(result, self.stage.process(self.p.i_data))
1209
1210         # connect previous rdy/valid/data - do cat on i_data
1211         # NOTE: cannot do the PrevControl-looking trick because
1212         # of need to process the data.  shaaaame....
1213         m.d.comb += [fifo.we.eq(self.p.i_valid_test),
1214                      self.p.o_ready.eq(fifo.writable),
1215                      eq(fifo.din, cat(result)),
1216                    ]
1217
1218         # connect next rdy/valid/data - do cat on o_data
1219         connections = [self.n.o_valid.eq(fifo.readable),
1220                      fifo.re.eq(self.n.i_ready_test),
1221                    ]
1222         if self.fwft or self.buffered:
1223             m.d.comb += connections
1224         else:
1225             m.d.sync += connections # unbuffered fwft mode needs sync
1226         o_data = cat(self.n.o_data).eq(fifo.dout)
1227         o_data = self._postprocess(o_data)
1228         m.d.comb += o_data
1229
1230         return m
1231
1232
1233 # aka "RegStage".
1234 class UnbufferedPipeline(FIFOControl):
1235     def __init__(self, stage, in_multi=None, stage_ctl=False):
1236         FIFOControl.__init__(self, 1, stage, in_multi, stage_ctl,
1237                                    fwft=True, pipe=False)
1238
1239 # aka "BreakReadyStage" XXX had to set fwft=True to get it to work
1240 class PassThroughHandshake(FIFOControl):
1241     def __init__(self, stage, in_multi=None, stage_ctl=False):
1242         FIFOControl.__init__(self, 1, stage, in_multi, stage_ctl,
1243                                    fwft=True, pipe=True)
1244
1245 # this is *probably* BufferedHandshake, although test #997 now succeeds.
1246 class BufferedHandshake(FIFOControl):
1247     def __init__(self, stage, in_multi=None, stage_ctl=False):
1248         FIFOControl.__init__(self, 2, stage, in_multi, stage_ctl,
1249                                    fwft=True, pipe=False)
1250
1251
1252 """
1253 # this is *probably* SimpleHandshake (note: memory cell size=0)
1254 class SimpleHandshake(FIFOControl):
1255     def __init__(self, stage, in_multi=None, stage_ctl=False):
1256         FIFOControl.__init__(self, 0, stage, in_multi, stage_ctl,
1257                                    fwft=True, pipe=False)
1258 """