src/arch/power/tlb.cc

   1 /*
   2  * Copyright (c) 2001-2005 The Regents of The University of Michigan
   3  * Copyright (c) 2007 MIPS Technologies, Inc.
   4  * Copyright (c) 2007-2008 The Florida State University
   5  * Copyright (c) 2009 The University of Edinburgh
   6  * All rights reserved.
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions are
  10  * met: redistributions of source code must retain the above copyright
  11  * notice, this list of conditions and the following disclaimer;
  12  * redistributions in binary form must reproduce the above copyright
  13  * notice, this list of conditions and the following disclaimer in the
  14  * documentation and/or other materials provided with the distribution;
  15  * neither the name of the copyright holders nor the names of its
  16  * contributors may be used to endorse or promote products derived from
  17  * this software without specific prior written permission.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  20  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  21  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  22  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  23  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  24  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  25  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  26  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  27  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  28  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  29  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  30  *
  31  * Authors: Nathan Binkert
  32  *          Steve Reinhardt
  33  *          Jaidev Patwardhan
  34  *          Stephen Hines
  35  *          Timothy M. Jones
  36  */
  37
  38 #include <string>
  39 #include <vector>
  40
  41 #include "arch/power/faults.hh"
  42 #include "arch/power/pagetable.hh"
  43 #include "arch/power/tlb.hh"
  44 #include "arch/power/utility.hh"
  45 #include "base/inifile.hh"
  46 #include "base/str.hh"
  47 #include "base/trace.hh"
  48 #include "cpu/thread_context.hh"
  49 #include "debug/Power.hh"
  50 #include "debug/TLB.hh"
  51 #include "mem/page_table.hh"
  52 #include "params/PowerTLB.hh"
  53 #include "sim/full_system.hh"
  54 #include "sim/process.hh"
  55
  56 using namespace std;
  57 using namespace PowerISA;
  58
  59 ///////////////////////////////////////////////////////////////////////
  60 //
  61 //  POWER TLB
  62 //
  63
  64 #define MODE2MASK(X) (1 << (X))
  65
  66 TLB::TLB(const Params *p)
  67     : BaseTLB(p), size(p->size), nlu(0)
  68 {
  69     table = new PowerISA::PTE[size];
  70     memset(table, 0, sizeof(PowerISA::PTE[size]));
  71     smallPages = 0;
  72 }
  73
  74 TLB::~TLB()
  75 {
  76     if (table)
  77         delete [] table;
  78 }
  79
  80 // look up an entry in the TLB
  81 PowerISA::PTE *
  82 TLB::lookup(Addr vpn, uint8_t asn) const
  83 {
  84     // assume not found...
  85     PowerISA::PTE *retval = NULL;
  86     PageTable::const_iterator i = lookupTable.find(vpn);
  87     if (i != lookupTable.end()) {
  88         while (i->first == vpn) {
  89             int index = i->second;
  90             PowerISA::PTE *pte = &table[index];
  91             Addr Mask = pte->Mask;
  92             Addr InvMask = ~Mask;
  93             Addr VPN  = pte->VPN;
  94             if (((vpn & InvMask) == (VPN & InvMask))
  95                && (pte->G  || (asn == pte->asid))) {
  96
  97                 // We have a VPN + ASID Match
  98                 retval = pte;
  99                 break;
 100             }
 101             ++i;
 102         }
 103     }
 104
 105     DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn,
 106             retval ? "hit" : "miss", retval ? retval->PFN1 : 0);
 107     return retval;
 108 }
 109
 110 PowerISA::PTE*
 111 TLB::getEntry(unsigned Index) const
 112 {
 113     // Make sure that Index is valid
 114     assert(Index<size);
 115     return &table[Index];
 116 }
 117
 118 int
 119 TLB::probeEntry(Addr vpn,uint8_t asn) const
 120 {
 121     // assume not found...
 122     int Ind = -1;
 123     PageTable::const_iterator i = lookupTable.find(vpn);
 124     if (i != lookupTable.end()) {
 125         while (i->first == vpn) {
 126             int index = i->second;
 127             PowerISA::PTE *pte = &table[index];
 128             Addr Mask = pte->Mask;
 129             Addr InvMask = ~Mask;
 130             Addr VPN  = pte->VPN;
 131             if (((vpn & InvMask) == (VPN & InvMask))
 132                 && (pte->G  || (asn == pte->asid))) {
 133
 134                 // We have a VPN + ASID Match
 135                 Ind = index;
 136                 break;
 137             }
 138             ++i;
 139         }
 140     }
 141
 142     DPRINTF(Power, "VPN: %x, asid: %d, Result of TLBP: %d\n", vpn, asn, Ind);
 143     return Ind;
 144 }
 145
 146 inline Fault
 147 TLB::checkCacheability(RequestPtr &req)
 148 {
 149     Addr VAddrUncacheable = 0xA0000000;
 150     if ((req->getVaddr() & VAddrUncacheable) == VAddrUncacheable) {
 151
 152         // mark request as uncacheable
 153         req->setFlags(Request::UNCACHEABLE);
 154     }
 155     return NoFault;
 156 }
 157
 158 void
 159 TLB::insertAt(PowerISA::PTE &pte, unsigned Index, int _smallPages)
 160 {
 161     smallPages=_smallPages;
 162     if (Index > size){
 163         warn("Attempted to write at index (%d) beyond TLB size (%d)",
 164              Index, size);
 165     } else {
 166
 167         // Update TLB
 168         if (table[Index].V0 || table[Index].V1) {
 169
 170             // Previous entry is valid
 171             PageTable::iterator i = lookupTable.find(table[Index].VPN);
 172             lookupTable.erase(i);
 173         }
 174         table[Index]=pte;
 175
 176         // Update fast lookup table
 177         lookupTable.insert(make_pair(table[Index].VPN, Index));
 178     }
 179 }
 180
 181 // insert a new TLB entry
 182 void
 183 TLB::insert(Addr addr, PowerISA::PTE &pte)
 184 {
 185     fatal("TLB Insert not yet implemented\n");
 186 }
 187
 188 void
 189 TLB::flushAll()
 190 {
 191     DPRINTF(TLB, "flushAll\n");
 192     memset(table, 0, sizeof(PowerISA::PTE[size]));
 193     lookupTable.clear();
 194     nlu = 0;
 195 }
 196
 197 void
 198 TLB::serialize(ostream &os)
 199 {
 200     SERIALIZE_SCALAR(size);
 201     SERIALIZE_SCALAR(nlu);
 202
 203     for (int i = 0; i < size; i++) {
 204         nameOut(os, csprintf("%s.PTE%d", name(), i));
 205         table[i].serialize(os);
 206     }
 207 }
 208
 209 void
 210 TLB::unserialize(Checkpoint *cp, const string &section)
 211 {
 212     UNSERIALIZE_SCALAR(size);
 213     UNSERIALIZE_SCALAR(nlu);
 214
 215     for (int i = 0; i < size; i++) {
 216         table[i].unserialize(cp, csprintf("%s.PTE%d", section, i));
 217         if (table[i].V0 || table[i].V1) {
 218             lookupTable.insert(make_pair(table[i].VPN, i));
 219         }
 220     }
 221 }
 222
 223 void
 224 TLB::regStats()
 225 {
 226     read_hits
 227         .name(name() + ".read_hits")
 228         .desc("DTB read hits")
 229         ;
 230
 231     read_misses
 232         .name(name() + ".read_misses")
 233         .desc("DTB read misses")
 234         ;
 235
 236
 237     read_accesses
 238         .name(name() + ".read_accesses")
 239         .desc("DTB read accesses")
 240         ;
 241
 242     write_hits
 243         .name(name() + ".write_hits")
 244         .desc("DTB write hits")
 245         ;
 246
 247     write_misses
 248         .name(name() + ".write_misses")
 249         .desc("DTB write misses")
 250         ;
 251
 252
 253     write_accesses
 254         .name(name() + ".write_accesses")
 255         .desc("DTB write accesses")
 256         ;
 257
 258     hits
 259         .name(name() + ".hits")
 260         .desc("DTB hits")
 261         ;
 262
 263     misses
 264         .name(name() + ".misses")
 265         .desc("DTB misses")
 266         ;
 267
 268     accesses
 269         .name(name() + ".accesses")
 270         .desc("DTB accesses")
 271         ;
 272
 273     hits = read_hits + write_hits;
 274     misses = read_misses + write_misses;
 275     accesses = read_accesses + write_accesses;
 276 }
 277
 278 Fault
 279 TLB::translateInst(RequestPtr req, ThreadContext *tc)
 280 {
 281     // Instruction accesses must be word-aligned
 282     if (req->getVaddr() & 0x3) {
 283         DPRINTF(TLB, "Alignment Fault on %#x, size = %d\n", req->getVaddr(),
 284                 req->getSize());
 285         return new AlignmentFault();
 286     }
 287
 288      Process * p = tc->getProcessPtr();
 289
 290      Fault fault = p->pTable->translate(req);
 291     if (fault != NoFault)
 292         return fault;
 293
 294     return NoFault;
 295 }
 296
 297 Fault
 298 TLB::translateData(RequestPtr req, ThreadContext *tc, bool write)
 299 {
 300     Process * p = tc->getProcessPtr();
 301
 302     Fault fault = p->pTable->translate(req);
 303     if (fault != NoFault)
 304         return fault;
 305
 306     return NoFault;
 307 }
 308
 309 Fault
 310 TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
 311 {
 312     if (FullSystem)
 313         fatal("translate atomic not yet implemented in full system mode.\n");
 314
 315     if (mode == Execute)
 316         return translateInst(req, tc);
 317     else
 318         return translateData(req, tc, mode == Write);
 319 }
 320
 321 void
 322 TLB::translateTiming(RequestPtr req, ThreadContext *tc,
 323                      Translation *translation, Mode mode)
 324 {
 325     assert(translation);
 326     translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
 327 }
 328
 329 Fault
 330 TLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode)
 331 {
 332     panic("Not implemented\n");
 333     return NoFault;
 334 }
 335
 336 Fault
 337 TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const
 338 {
 339     return NoFault;
 340 }
 341
 342 PowerISA::PTE &
 343 TLB::index(bool advance)
 344 {
 345     PowerISA::PTE *pte = &table[nlu];
 346
 347     if (advance)
 348         nextnlu();
 349
 350     return *pte;
 351 }
 352
 353 PowerISA::TLB *
 354 PowerTLBParams::create()
 355 {
 356     return new PowerISA::TLB(this);
 357 }