1 from nmigen
.compat
.sim
import run_simulation
2 from nmigen
.cli
import verilog
, rtlil
3 from nmigen
import Signal
, Module
, Elaboratable
6 class SRLatch(Elaboratable
):
8 self
.s
= Signal(reset_less
=True)
9 self
.r
= Signal(reset_less
=True)
10 self
.q
= Signal(reset_less
=True)
11 self
.qn
= Signal(reset_less
=True)
13 def elaborate(self
, platform
):
15 q_int
= Signal(reset_less
=True)
16 qn_int
= Signal(reset_less
=True)
18 m
.d
.comb
+= self
.q
.eq(~
(self
.s | qn_int
))
19 m
.d
.comb
+= self
.qn
.eq(~
(self
.r | q_int
))
21 m
.d
.sync
+= q_int
.eq(self
.q
)
22 m
.d
.sync
+= qn_int
.eq(self
.qn
)
27 return self
.s
, self
.r
, self
.q
, self
.qn
46 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
47 with
open("test_srlatch.il", "w") as f
:
50 run_simulation(dut
, sr_sim(dut
), vcd_name
='test_srlatch.vcd')
52 if __name__
== '__main__':