src/nmutil/latch.py

   1 from nmigen.compat.sim import run_simulation
   2 from nmigen.cli import verilog, rtlil
   3 from nmigen import Signal, Module, Elaboratable
   4
   5
   6 class SRLatch(Elaboratable):
   7     def __init__(self):
   8         self.s = Signal(reset_less=True)
   9         self.r = Signal(reset_less=True)
  10         self.q = Signal(reset_less=True)
  11         self.qn = Signal(reset_less=True)
  12
  13     def elaborate(self, platform):
  14         m = Module()
  15         q_int = Signal(reset_less=True)
  16         qn_int = Signal(reset_less=True)
  17
  18         m.d.comb += self.q.eq(~(self.s | qn_int))
  19         m.d.comb += self.qn.eq(~(self.r | q_int))
  20
  21         m.d.sync += q_int.eq(self.q)
  22         m.d.sync += qn_int.eq(self.qn)
  23
  24         return m
  25
  26     def ports(self):
  27         return self.s, self.r, self.q, self.qn
  28
  29
  30 def sr_sim(dut):
  31     yield dut.s.eq(0)
  32     yield dut.r.eq(0)
  33     yield
  34     yield dut.s.eq(1)
  35     yield
  36     yield dut.s.eq(0)
  37     yield
  38     yield dut.r.eq(1)
  39     yield
  40     yield dut.r.eq(0)
  41     yield
  42     yield
  43
  44 def test_sr():
  45     dut = SRLatch()
  46     vl = rtlil.convert(dut, ports=dut.ports())
  47     with open("test_srlatch.il", "w") as f:
  48         f.write(vl)
  49
  50     run_simulation(dut, sr_sim(dut), vcd_name='test_srlatch.vcd')
  51
  52 if __name__ == '__main__':
  53     test_sr()