tercel/wishbone_spi_master.v

   1 // © 2017 - 2022 Raptor Engineering, LLC
   2 //
   3 // Released under the terms of the GNU LGPL v3
   4 // See the LICENSE file for full details
   5
   6 // =============================================================================================
   7 // Memory Map:
   8 // =============================================================================================
   9 // Device ID string (8 bytes)
  10 // Device version (4 bytes)
  11 // Base clock frequency (4 bytes)
  12 // PHY configuration register 1 (4 bytes): {cs_extra_idle_cycles, 2'b0, qspi_write_quad_io_en, qspi_read_quad_io_en, fast_read_mode, four_byte_address_mode, phy_io_type, dummy_cycle_count, spi_clock_divisor}
  13 // Flash configuration register 1 (4 bytes): {4BA QSPI read command, 3BA QSPI read command, 4BA SPI read command, 3BA SPI read command}
  14 // Flash configuration register 2 (4 bytes): {4BA QSPI fast read command, 3BA QSPI fast read command, 4BA SPI fast read command, 3BA SPI fast read command}
  15 // Flash configuration register 3 (4 bytes): {4BA QSPI program command, 3BA QSPI program command, 4BA SPI program command, 3BA SPI program command}
  16 // Flash configuration register 4 (4 bytes): {spi_cs_active_hold_cycles}
  17 // Flash configuration register 5 (4 bytes): {30'b0, allow_multicycle_writes, allow_multicycle_reads}
  18 // Control register 1 (4 bytes): {31'b0, user_command_mode}
  19 // Data register 1 (4 bytes): {24'b0, user_command_mode_read_during_write}
  20
  21 // Stop LiteX silently ignoring net naming / missing register errors
  22 `default_nettype none
  23
  24 module tercel_core(
  25                 // Configuration registers
  26                 input wire [31:0] sys_clk_freq,
  27
  28                 // Wishbone signals
  29                 input wire wishbone_cyc,
  30                 input wire wishbone_stb,
  31                 input wire wishbone_we,
  32                 input wire [29:0] wishbone_adr,
  33                 input wire [31:0] wishbone_dat_w,
  34                 output wire [31:0] wishbone_dat_r,
  35                 input wire [3:0] wishbone_sel,
  36                 output wire wishbone_ack,
  37                 output wire wishbone_err,
  38
  39                 // Wishbone configuration port signals
  40                 input wire cfg_wishbone_cyc,
  41                 input wire cfg_wishbone_stb,
  42                 input wire cfg_wishbone_we,
  43                 input wire [29:0] cfg_wishbone_adr,
  44                 input wire [31:0] cfg_wishbone_dat_w,
  45                 output wire [31:0] cfg_wishbone_dat_r,
  46                 input wire [3:0] cfg_wishbone_sel,
  47                 output wire cfg_wishbone_ack,
  48                 output wire cfg_wishbone_err,
  49
  50                 // SPI bus signals
  51                 output wire spi_clock,
  52                 output wire [3:0] spi_d_out,
  53                 output wire [3:0] spi_d_direction,                      // 0 == tristate (input), 1 == driven (output)
  54                 input wire [3:0] spi_d_in,
  55                 output wire spi_ss_n,
  56
  57                 output wire [7:0] debug_port,
  58
  59                 input wire peripheral_reset,
  60                 input wire peripheral_clock
  61         );
  62
  63         // Control and status registers
  64         wire [63:0] device_id;
  65         wire [31:0] device_version;
  66
  67         // PHY configuration register 1
  68         // Defaults to standard SPI mode, 3BA, non-extended read/write (qspi_[read|write]_quad_io_en = 0), cs_extra_idle_cycles = 0, dummy cycle cont = 10, clock divisor 16
  69         reg [31:0] phy_cfg1 = 32'h00000a10;
  70
  71         // Defaults to compatibility with Micron N25Q/512MB and similar 3BA/4BA capable devices, with multicycle and write disabled
  72         // Note that the N25Q does not support normal reads in QSPI mode, so we leave the QSPI normal read commands equal
  73         // to the normal SPI commands for safety -- no corruption is possible if the device is latched into read mode...
  74         reg [31:0] flash_cfg1 = 32'h13031303;
  75         reg [31:0] flash_cfg2 = 32'heceb0c0b;
  76         reg [31:0] flash_cfg3 = 32'h34321202;
  77         reg [31:0] flash_cfg4 = 32'h00000000;
  78         reg [31:0] flash_cfg5 = 32'h00000000;
  79
  80         // Defaults to read mode
  81         reg [31:0] core_ctl1 = 32'h00000000;
  82         wire [31:0] core_data1;
  83
  84         // Device identifier
  85         assign device_id = 64'h7c5250545350494d;
  86         assign device_version = 32'h00010000;
  87
  88         reg cfg_wishbone_ack_reg = 0;
  89         reg [31:0] cfg_wishbone_dat_r_reg = 0;
  90
  91         assign cfg_wishbone_ack = cfg_wishbone_ack_reg;
  92         assign cfg_wishbone_dat_r = cfg_wishbone_dat_r_reg;
  93
  94         parameter WB_CFG_TRANSFER_STATE_IDLE = 0;
  95         parameter WB_CFG_TRANSFER_STATE_TR01 = 1;
  96
  97         reg [31:0] wishbone_config_buffer_address_reg = 0;
  98         reg [7:0] wishbone_config_transfer_state = 0;
  99         reg [31:0] wishbone_cfg_space_tx_buffer = 0;
 100         reg [31:0] wishbone_cfg_space_rx_buffer = 0;
 101
 102         // Wishbone configuration space connector
 103         always @(posedge peripheral_clock) begin
 104                 if (peripheral_reset) begin
 105                         // Reset Wishbone interface / control state machine
 106                         cfg_wishbone_ack_reg <= 0;
 107
 108                         wishbone_config_transfer_state <= WB_CFG_TRANSFER_STATE_IDLE;
 109                 end else begin
 110                         case (wishbone_config_transfer_state)
 111                                 WB_CFG_TRANSFER_STATE_IDLE: begin
 112                                         // Compute effective address
 113                                         wishbone_config_buffer_address_reg[31:2] = cfg_wishbone_adr;
 114                                         case (cfg_wishbone_sel)
 115                                                 4'b0001: wishbone_config_buffer_address_reg[1:0] = 0;
 116                                                 4'b0010: wishbone_config_buffer_address_reg[1:0] = 1;
 117                                                 4'b0100: wishbone_config_buffer_address_reg[1:0] = 2;
 118                                                 4'b1000: wishbone_config_buffer_address_reg[1:0] = 3;
 119                                                 4'b1111: wishbone_config_buffer_address_reg[1:0] = 0;
 120                                                 default: wishbone_config_buffer_address_reg[1:0] = 0;
 121                                         endcase
 122
 123                                         if (cfg_wishbone_cyc && cfg_wishbone_stb) begin
 124                                                 // Configuration register space access
 125                                                 // Single clock pulse signals in deasserted state...process incoming request!
 126                                                 if (!cfg_wishbone_we) begin
 127                                                         // Read requested
 128                                                         case ({wishbone_config_buffer_address_reg[7:2], 2'b00})
 129                                                                 0: wishbone_cfg_space_tx_buffer = device_id[63:32];
 130                                                                 4: wishbone_cfg_space_tx_buffer = device_id[31:0];
 131                                                                 8: wishbone_cfg_space_tx_buffer = device_version;
 132                                                                 12: wishbone_cfg_space_tx_buffer = sys_clk_freq;
 133                                                                 16: wishbone_cfg_space_tx_buffer = phy_cfg1;
 134                                                                 20: wishbone_cfg_space_tx_buffer = flash_cfg1;
 135                                                                 24: wishbone_cfg_space_tx_buffer = flash_cfg2;
 136                                                                 28: wishbone_cfg_space_tx_buffer = flash_cfg3;
 137                                                                 32: wishbone_cfg_space_tx_buffer = flash_cfg4;
 138                                                                 36: wishbone_cfg_space_tx_buffer = flash_cfg5;
 139                                                                 40: wishbone_cfg_space_tx_buffer = core_ctl1;
 140                                                                 44: wishbone_cfg_space_tx_buffer = core_data1;
 141                                                                 default: wishbone_cfg_space_tx_buffer = 0;
 142                                                         endcase
 143
 144                                                         // Endian swap
 145                                                         cfg_wishbone_dat_r_reg[31:24] <= wishbone_cfg_space_tx_buffer[7:0];
 146                                                         cfg_wishbone_dat_r_reg[23:16] <= wishbone_cfg_space_tx_buffer[15:8];
 147                                                         cfg_wishbone_dat_r_reg[15:8] <= wishbone_cfg_space_tx_buffer[23:16];
 148                                                         cfg_wishbone_dat_r_reg[7:0] <= wishbone_cfg_space_tx_buffer[31:24];
 149
 150                                                         // Signal transfer complete
 151                                                         cfg_wishbone_ack_reg <= 1;
 152
 153                                                         wishbone_config_transfer_state <= WB_CFG_TRANSFER_STATE_TR01;
 154                                                 end else begin
 155                                                         // Write requested
 156                                                         case ({wishbone_config_buffer_address_reg[7:2], 2'b00})
 157                                                                 // Device ID / version registers cannot be written, don't even try...
 158                                                                 16: wishbone_cfg_space_rx_buffer = phy_cfg1;
 159                                                                 20: wishbone_cfg_space_rx_buffer = flash_cfg1;
 160                                                                 24: wishbone_cfg_space_rx_buffer = flash_cfg2;
 161                                                                 28: wishbone_cfg_space_rx_buffer = flash_cfg3;
 162                                                                 32: wishbone_cfg_space_rx_buffer = flash_cfg4;
 163                                                                 36: wishbone_cfg_space_rx_buffer = flash_cfg5;
 164                                                                 40: wishbone_cfg_space_rx_buffer = core_ctl1;
 165                                                                 // Status registers cannot be written, don't even try...
 166                                                                 default: wishbone_cfg_space_rx_buffer = 0;
 167                                                         endcase
 168
 169                                                         if (cfg_wishbone_sel[0]) begin
 170                                                                 wishbone_cfg_space_rx_buffer[7:0] = cfg_wishbone_dat_w[31:24];
 171                                                         end
 172                                                         if (cfg_wishbone_sel[1]) begin
 173                                                                 wishbone_cfg_space_rx_buffer[15:8] = cfg_wishbone_dat_w[23:16];
 174                                                         end
 175                                                         if (cfg_wishbone_sel[2]) begin
 176                                                                 wishbone_cfg_space_rx_buffer[23:16] = cfg_wishbone_dat_w[15:8];
 177                                                         end
 178                                                         if (cfg_wishbone_sel[3]) begin
 179                                                                 wishbone_cfg_space_rx_buffer[31:24] = cfg_wishbone_dat_w[7:0];
 180                                                         end
 181
 182                                                         case ({wishbone_config_buffer_address_reg[7:2], 2'b00})
 183                                                                 16: phy_cfg1 <= wishbone_cfg_space_rx_buffer;
 184                                                                 20: flash_cfg1 <= wishbone_cfg_space_rx_buffer;
 185                                                                 24: flash_cfg2 <= wishbone_cfg_space_rx_buffer;
 186                                                                 28: flash_cfg3 <= wishbone_cfg_space_rx_buffer;
 187                                                                 32: flash_cfg4 <= wishbone_cfg_space_rx_buffer;
 188                                                                 36: flash_cfg5 <= wishbone_cfg_space_rx_buffer;
 189                                                                 40: core_ctl1 <= wishbone_cfg_space_rx_buffer;
 190                                                         endcase
 191
 192                                                         // Signal transfer complete
 193                                                         cfg_wishbone_ack_reg <= 1;
 194
 195                                                         wishbone_config_transfer_state <= WB_CFG_TRANSFER_STATE_TR01;
 196                                                 end
 197                                         end
 198                                 end
 199                                 WB_CFG_TRANSFER_STATE_TR01: begin
 200                                         // Cycle complete
 201                                         cfg_wishbone_ack_reg <= 0;
 202                                         wishbone_config_transfer_state <= WB_CFG_TRANSFER_STATE_IDLE;
 203                                 end
 204                                 default: begin
 205                                         // Should never reach this state
 206                                         wishbone_config_transfer_state <= WB_CFG_TRANSFER_STATE_IDLE;
 207                                 end
 208                         endcase
 209                 end
 210         end
 211
 212         // SPI bus signals
 213         wire spi_data_direction;
 214         wire spi_quad_mode_pin_enable;
 215         wire drive_host_interfaces;
 216         assign drive_host_interfaces = 1;
 217         assign spi_d_direction[0] = !spi_quad_mode_pin_enable || (spi_data_direction & drive_host_interfaces);
 218         assign spi_d_direction[1] = spi_quad_mode_pin_enable && (spi_data_direction & drive_host_interfaces);
 219         assign spi_d_direction[2] = !spi_quad_mode_pin_enable || (spi_data_direction & drive_host_interfaces);
 220         assign spi_d_direction[3] = !spi_quad_mode_pin_enable || (spi_data_direction & drive_host_interfaces);
 221
 222         // Interface registers
 223         wire [7:0] spi_clock_divisor;
 224         wire [7:0] dummy_cycle_count;
 225         wire [1:0] phy_io_type;
 226         wire [7:0] cs_extra_idle_cycles;
 227         wire four_byte_address_mode;
 228         wire fast_read_mode;
 229         wire qspi_read_quad_io_en;
 230         wire qspi_write_quad_io_en;
 231         wire [7:0] qspi_read_4ba_command_code;
 232         wire [7:0] qspi_read_3ba_command_code;
 233         wire [7:0] spi_read_4ba_command_code;
 234         wire [7:0] spi_read_3ba_command_code;
 235         wire [7:0] qspi_fast_read_4ba_command_code;
 236         wire [7:0] qspi_fast_read_3ba_command_code;
 237         wire [7:0] spi_fast_read_4ba_command_code;
 238         wire [7:0] spi_fast_read_3ba_command_code;
 239         wire [7:0] qspi_program_4ba_command_code;
 240         wire [7:0] qspi_program_3ba_command_code;
 241         wire [7:0] spi_program_4ba_command_code;
 242         wire [7:0] spi_program_3ba_command_code;
 243         wire [31:0] spi_cs_active_hold_cycles;
 244         wire allow_multicycle_writes;
 245         wire allow_multicycle_reads;
 246         wire user_command_mode;
 247         reg [7:0] user_command_mode_read_during_write = 0;
 248         assign spi_clock_divisor = phy_cfg1[7:0];
 249         assign dummy_cycle_count = phy_cfg1[15:8];
 250         assign phy_io_type = phy_cfg1[17:16];
 251         assign cs_extra_idle_cycles = phy_cfg1[31:24];
 252         assign four_byte_address_mode = phy_cfg1[18];
 253         assign fast_read_mode = phy_cfg1[19];
 254         assign qspi_read_quad_io_en = phy_cfg1[20];
 255         assign qspi_write_quad_io_en = phy_cfg1[21];
 256         assign qspi_read_4ba_command_code = flash_cfg1[31:24];
 257         assign qspi_read_3ba_command_code = flash_cfg1[23:16];
 258         assign spi_read_4ba_command_code = flash_cfg1[15:8];
 259         assign spi_read_3ba_command_code = flash_cfg1[7:0];
 260         assign qspi_fast_read_4ba_command_code = flash_cfg2[31:24];
 261         assign qspi_fast_read_3ba_command_code = flash_cfg2[23:16];
 262         assign spi_fast_read_4ba_command_code = flash_cfg2[15:8];
 263         assign spi_fast_read_3ba_command_code = flash_cfg2[7:0];
 264         assign qspi_program_4ba_command_code = flash_cfg3[31:24];
 265         assign qspi_program_3ba_command_code = flash_cfg3[23:16];
 266         assign spi_program_4ba_command_code = flash_cfg3[15:8];
 267         assign spi_program_3ba_command_code = flash_cfg3[7:0];
 268         assign spi_cs_active_hold_cycles = flash_cfg4[31:0];
 269         assign allow_multicycle_writes = flash_cfg5[1];
 270         assign allow_multicycle_reads = flash_cfg5[0];
 271         assign user_command_mode = core_ctl1[0];
 272         assign core_data1 = {24'h000000, user_command_mode_read_during_write};
 273
 274         parameter PHY_IO_TYPE_SINGLE = 0;
 275         parameter PHY_IO_TYPE_QUAD = 2;
 276
 277         // PHY clock generator and reset synchronizer
 278         // Divisor:
 279         // (spi_clock_divisor - 1) * 2
 280         // 0 == undefined (actually divide by two)
 281         // 1 == divide by 1
 282         // 2 == divide by 2
 283         // 3 == divide by 4
 284         // 4 == divide by 6
 285         // 5 == divide by 8
 286         // 6 == divide by 10
 287         // 7 == divide by 12
 288         // etc.
 289         reg phy_reset = 0;
 290         wire spi_phy_clock;
 291         reg spi_phy_clock_gen_reg = 0;
 292         reg spi_phy_clock_gen_reg_prev = 0;
 293         reg [7:0] spi_phy_clock_counter = 0;
 294         assign spi_phy_clock = (spi_clock_divisor == 1)?peripheral_clock:spi_phy_clock_gen_reg;
 295         always @(posedge peripheral_clock) begin
 296                 // Clock generator
 297                 if (spi_phy_clock_counter >= (spi_clock_divisor - 2)) begin
 298                         spi_phy_clock_gen_reg <= ~spi_phy_clock_gen_reg;
 299                         spi_phy_clock_counter <= 0;
 300                 end else begin
 301                         spi_phy_clock_counter <= spi_phy_clock_counter + 1;
 302                 end
 303
 304                 // Reset synchronizer
 305                 if ((spi_phy_clock_gen_reg_prev == 0) && (spi_phy_clock_gen_reg == 1)) begin
 306                         phy_reset <= 0;
 307                 end else begin
 308                         if (peripheral_reset) begin
 309                                 phy_reset <= 1;
 310                         end
 311                 end
 312
 313                 spi_phy_clock_gen_reg_prev <= spi_phy_clock_gen_reg;
 314         end
 315
 316         wire phy_ready;
 317         reg [31:0] phy_tx_data = 0;
 318         wire [31:0] phy_rx_data;
 319         reg phy_hold_ss_active = 0;
 320         reg phy_qspi_mode_active = 0;
 321         reg phy_qspi_transfer_mode = 0;
 322         reg phy_qspi_transfer_direction = 0;
 323         reg [7:0] phy_dummy_cycle_count = 0;
 324         reg [3:0] single_cycle_read_counter = 0;
 325         reg [3:0] single_cycle_write_counter = 0;
 326         reg phy_cycle_start = 0;
 327         wire phy_transaction_complete;
 328
 329         spi_master_phy_quad spi_master_phy_quad(
 330                 .platform_clock(spi_phy_clock),
 331                 .reset(phy_reset),
 332                 .ready(phy_ready),
 333                 .tx_data(phy_tx_data),
 334                 .rx_data(phy_rx_data),
 335                 .dummy_cycle_count(phy_dummy_cycle_count),
 336                 .hold_ss_active(phy_hold_ss_active),
 337                 .qspi_mode_active(phy_qspi_mode_active),
 338                 .qspi_transfer_mode(phy_qspi_transfer_mode),
 339                 .qspi_transfer_direction(phy_qspi_transfer_direction),
 340                 .cycle_start(phy_cycle_start),
 341                 .transaction_complete(phy_transaction_complete),
 342
 343                 .spi_clock(spi_clock),
 344                 .spi_d0_out(spi_d_out[0]),
 345                 .spi_d0_in(spi_d_in[0]),
 346                 .spi_d1_out(spi_d_out[1]),
 347                 .spi_d1_in(spi_d_in[1]),
 348                 .spi_d2_out(spi_d_out[2]),
 349                 .spi_d2_in(spi_d_in[2]),
 350                 .spi_d3_out(spi_d_out[3]),
 351                 .spi_d3_in(spi_d_in[3]),
 352                 .spi_ss_n(spi_ss_n),
 353                 .spi_data_direction(spi_data_direction),
 354                 .spi_quad_mode_pin_enable(spi_quad_mode_pin_enable)
 355         );
 356
 357         reg [3:0] wishbone_sel_reg = 0;
 358         reg wishbone_ack_reg = 0;
 359         assign wishbone_ack = wishbone_ack_reg;
 360         reg [31:0] wishbone_dat_r_reg = 0;
 361         assign wishbone_dat_r = wishbone_dat_r_reg;
 362
 363         parameter SPI_MASTER_TRANSFER_STATE_PHYI = 0;
 364         parameter SPI_MASTER_TRANSFER_STATE_IDLE = 1;
 365         parameter SPI_MASTER_TRANSFER_STATE_TR01 = 2;
 366         parameter SPI_MASTER_TRANSFER_STATE_TR02 = 3;
 367         parameter SPI_MASTER_TRANSFER_STATE_TR03 = 16;
 368         parameter SPI_MASTER_TRANSFER_STATE_TR04 = 17;
 369         parameter SPI_MASTER_TRANSFER_STATE_TR05 = 18;
 370         parameter SPI_MASTER_TRANSFER_STATE_TR06 = 19;
 371         parameter SPI_MASTER_TRANSFER_STATE_TR07 = 20;
 372         parameter SPI_MASTER_TRANSFER_STATE_TR08 = 21;
 373         parameter SPI_MASTER_TRANSFER_STATE_TR09 = 22;
 374         parameter SPI_MASTER_TRANSFER_STATE_TR10 = 23;
 375         parameter SPI_MASTER_TRANSFER_STATE_TR11 = 24;
 376         parameter SPI_MASTER_TRANSFER_STATE_TR12 = 25;
 377         parameter SPI_MASTER_TRANSFER_STATE_RD01 = 32;
 378         parameter SPI_MASTER_TRANSFER_STATE_RD02 = 33;
 379         parameter SPI_MASTER_TRANSFER_STATE_RD03 = 34;
 380         parameter SPI_MASTER_TRANSFER_STATE_WR01 = 48;
 381         parameter SPI_MASTER_TRANSFER_STATE_WR02 = 49;
 382         parameter SPI_MASTER_TRANSFER_STATE_WR03 = 50;
 383         parameter SPI_MASTER_TRANSFER_STATE_UC01 = 64;
 384         parameter SPI_MASTER_TRANSFER_STATE_UC02 = 65;
 385         parameter SPI_MASTER_TRANSFER_STATE_UC03 = 66;
 386         parameter SPI_MASTER_TRANSFER_STATE_UC04 = 67;
 387
 388         reg [7:0] byte_out = 0;
 389         reg [7:0] spi_transfer_state = 0;
 390         reg spi_data_cycle_type = 0;
 391         reg [31:0] spi_address_reg = 0;
 392         reg [1:0] phy_io_type_reg;
 393         reg [31:0] spi_byte_read_count = 0;
 394         reg wishbone_data_cycle_type = 0;
 395         reg wishbone_access_is_32_bits = 0;
 396         reg user_command_mode_active = 0;
 397         reg multicycle_read_in_progress = 0;
 398         reg multicycle_write_in_progress = 0;
 399         reg [31:0] multicycle_transaction_address = 0;
 400         reg [7:0] cs_extra_cycle_counter = 0;
 401         reg [31:0] spi_cs_active_counter = 0;
 402
 403         assign debug_port = spi_transfer_state;
 404
 405         always @(posedge peripheral_clock) begin
 406                 if (peripheral_reset) begin
 407                         // Reset PHY
 408                         phy_hold_ss_active <= 0;
 409                         phy_qspi_mode_active <= 0;
 410                         phy_qspi_transfer_mode <= 0;
 411                         phy_qspi_transfer_direction <= 0;
 412                         phy_dummy_cycle_count <= 0;
 413                         phy_cycle_start <= 0;
 414
 415                         // Reset Wishbone interface / control state machine
 416                         wishbone_ack_reg <= 0;
 417                         wishbone_data_cycle_type <= 0;
 418                         wishbone_access_is_32_bits <= 0;
 419                         user_command_mode_read_during_write <= 0;
 420                         user_command_mode_active <= 0;
 421                         multicycle_read_in_progress <= 0;
 422                         multicycle_write_in_progress <= 0;
 423                         multicycle_transaction_address <= 0;
 424                         spi_cs_active_counter <= 0;
 425                         spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_PHYI;
 426                 end else begin
 427                         case (spi_transfer_state)
 428                                 SPI_MASTER_TRANSFER_STATE_PHYI: begin
 429                                         if (phy_ready && (!phy_reset)) begin
 430                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_IDLE;
 431                                         end
 432                                 end
 433                                 SPI_MASTER_TRANSFER_STATE_IDLE: begin
 434                                         // Compute effective address
 435                                         spi_address_reg[31:2] = wishbone_adr;
 436                                         case (wishbone_sel)
 437                                                 4'b0001: spi_address_reg[1:0] = 0;
 438                                                 4'b0010: spi_address_reg[1:0] = 1;
 439                                                 4'b0100: spi_address_reg[1:0] = 2;
 440                                                 4'b1000: spi_address_reg[1:0] = 3;
 441                                                 4'b1111: spi_address_reg[1:0] = 0;
 442                                                 default: spi_address_reg[1:0] = 0;
 443                                         endcase
 444
 445                                         // Process command
 446                                         if ((spi_cs_active_hold_cycles > 0) && (spi_cs_active_counter >= spi_cs_active_hold_cycles)) begin
 447                                                 // Stop multicycle transfer
 448                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_UC02;
 449                                         end else if (!user_command_mode && user_command_mode_active) begin
 450                                                 // Exit user command mode
 451                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_UC02;
 452                                         end else if (multicycle_read_in_progress) begin
 453                                                 if (!allow_multicycle_reads) begin
 454                                                         // Stop multicycle transfer
 455                                                         spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_UC02;
 456                                                 end else if (wishbone_cyc && wishbone_stb) begin
 457                                                         if (user_command_mode) begin
 458                                                                 // User command mode requested
 459                                                                 // Stop multicycle transfer in preparation to enable user command mode
 460                                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_UC02;
 461                                                         end else if (wishbone_data_cycle_type) begin
 462                                                                 // Write requested
 463                                                                 // Stop multicycle transfer in preparation to enable write mode
 464                                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_UC02;
 465                                                         end else begin
 466                                                                 // Select 8-bit/32-bit transfer size via Wishbone access mode
 467                                                                 if (wishbone_sel == 4'b1111) begin
 468                                                                         wishbone_access_is_32_bits <= 1;
 469                                                                 end else begin
 470                                                                         wishbone_access_is_32_bits <= 0;
 471                                                                 end
 472                                                                 wishbone_sel_reg <= wishbone_sel;
 473
 474                                                                 // Verify next address matches current address
 475                                                                 if (four_byte_address_mode) begin
 476                                                                         if (multicycle_transaction_address == spi_address_reg) begin
 477                                                                                 // Transfer next data chunk
 478                                                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_RD01;
 479                                                                         end else begin
 480                                                                                 // Stop multicycle transfer
 481                                                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_UC02;
 482                                                                         end
 483                                                                 end else begin
 484                                                                         if (multicycle_transaction_address[23:0] == spi_address_reg[23:0]) begin
 485                                                                                 // Transfer next data chunk
 486                                                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_RD01;
 487                                                                         end else begin
 488                                                                                 // Stop multicycle transfer
 489                                                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_UC02;
 490                                                                         end
 491                                                                 end
 492                                                         end
 493                                                 end
 494                                         end else if (multicycle_write_in_progress) begin
 495                                                 if (!allow_multicycle_writes) begin
 496                                                         // Stop multicycle transfer
 497                                                         spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_UC02;
 498                                                 end else if (wishbone_cyc && wishbone_stb) begin
 499                                                         if (user_command_mode) begin
 500                                                                 // User command mode requested
 501                                                                 // Stop multicycle transfer in preparation to enable user command mode
 502                                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_UC02;
 503                                                         end else if (!wishbone_data_cycle_type) begin
 504                                                                 // Read requested
 505                                                                 // Stop multicycle transfer in preparation to enable read mode
 506                                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_UC02;
 507                                                         end else begin
 508                                                                 // Select 8-bit/32-bit transfer size via Wishbone access mode
 509                                                                 if (wishbone_sel == 4'b1111) begin
 510                                                                         wishbone_access_is_32_bits <= 1;
 511                                                                 end else begin
 512                                                                         wishbone_access_is_32_bits <= 0;
 513                                                                 end
 514                                                                 wishbone_sel_reg <= wishbone_sel;
 515
 516                                                                 // Verify next address matches current address
 517                                                                 if (four_byte_address_mode) begin
 518                                                                         if (multicycle_transaction_address == spi_address_reg) begin
 519                                                                                 // Transfer next data chunk
 520                                                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_WR01;
 521                                                                         end else begin
 522                                                                                 // Stop multicycle transfer
 523                                                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_UC02;
 524                                                                         end
 525                                                                 end else begin
 526                                                                         if (multicycle_transaction_address[23:0] == spi_address_reg[23:0]) begin
 527                                                                                 // Transfer next data chunk
 528                                                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_WR01;
 529                                                                         end else begin
 530                                                                                 // Stop multicycle transfer
 531                                                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_UC02;
 532                                                                         end
 533                                                                 end
 534                                                         end
 535                                                 end
 536                                         end else begin
 537                                                 if (wishbone_cyc && wishbone_stb) begin
 538                                                         if (wishbone_sel == 4'b1111) begin
 539                                                                 wishbone_access_is_32_bits <= 1;
 540                                                         end else begin
 541                                                                 wishbone_access_is_32_bits <= 0;
 542                                                         end
 543                                                         wishbone_sel_reg <= wishbone_sel;
 544                                                         wishbone_data_cycle_type <= wishbone_we;
 545                                                         phy_io_type_reg <= phy_io_type;
 546                                                         if (!phy_transaction_complete) begin
 547                                                                 if (user_command_mode) begin
 548                                                                         // Read the data byte to write from the active lane
 549                                                                         if (wishbone_sel[0]) begin
 550                                                                                 phy_tx_data[7:0] <= wishbone_dat_w[31:24];
 551                                                                         end else if (wishbone_sel[1]) begin
 552                                                                                 phy_tx_data[7:0] <= wishbone_dat_w[23:16];
 553                                                                         end else if (wishbone_sel[2]) begin
 554                                                                                 phy_tx_data[7:0] <= wishbone_dat_w[15:8];
 555                                                                         end else if (wishbone_sel[3]) begin
 556                                                                                 phy_tx_data[7:0] <= wishbone_dat_w[7:0];
 557                                                                         end else begin
 558                                                                                 phy_tx_data[7:0] = 8'hff;       // Safe default -- will not send any useful commands / data
 559                                                                         end
 560
 561                                                                         // Set up SPI access
 562                                                                         phy_tx_data[31:8] = 0;
 563                                                                         phy_qspi_mode_active <= 0;
 564                                                                         phy_qspi_transfer_mode <= 0;
 565                                                                         phy_dummy_cycle_count <= 0;
 566                                                                         phy_hold_ss_active <= 1;
 567                                                                         phy_cycle_start <= 1;
 568
 569                                                                         // Set user command mode active
 570                                                                         user_command_mode_active <= 1;
 571                                                                         spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_UC01;
 572                                                                 end else begin
 573                                                                         if (!wishbone_we) begin
 574                                                                                 // Set up SPI read access
 575                                                                                 if (phy_io_type == PHY_IO_TYPE_QUAD) begin
 576                                                                                         if (four_byte_address_mode) begin
 577                                                                                                 if (fast_read_mode) begin
 578                                                                                                         phy_tx_data <= qspi_fast_read_4ba_command_code;
 579                                                                                                 end else begin
 580                                                                                                         phy_tx_data <= qspi_read_4ba_command_code;
 581                                                                                                 end
 582                                                                                         end else begin
 583                                                                                                 if (fast_read_mode) begin
 584                                                                                                         phy_tx_data <= qspi_fast_read_3ba_command_code;
 585                                                                                                 end else begin
 586                                                                                                         phy_tx_data <= qspi_read_3ba_command_code;
 587                                                                                                 end
 588                                                                                         end
 589                                                                                 end else begin
 590                                                                                         if (four_byte_address_mode) begin
 591                                                                                                 if (fast_read_mode) begin
 592                                                                                                         phy_tx_data <= spi_fast_read_4ba_command_code;
 593                                                                                                 end else begin
 594                                                                                                         phy_tx_data <= spi_read_4ba_command_code;
 595                                                                                                 end
 596                                                                                         end else begin
 597                                                                                                 if (fast_read_mode) begin
 598                                                                                                         phy_tx_data <= spi_fast_read_3ba_command_code;
 599                                                                                                 end else begin
 600                                                                                                         phy_tx_data <= spi_read_3ba_command_code;
 601                                                                                                 end
 602                                                                                         end
 603                                                                                 end
 604                                                                                 if (allow_multicycle_reads) begin
 605                                                                                         multicycle_read_in_progress <= 1;
 606                                                                                 end else begin
 607                                                                                         single_cycle_read_counter <= 0;
 608                                                                                 end
 609                                                                         end else begin
 610                                                                                 // Set up SPI write access
 611                                                                                 if (phy_io_type == PHY_IO_TYPE_QUAD) begin
 612                                                                                         if (four_byte_address_mode) begin
 613                                                                                                 phy_tx_data <= qspi_program_4ba_command_code;
 614                                                                                         end else begin
 615                                                                                                 phy_tx_data <= qspi_program_3ba_command_code;
 616                                                                                         end
 617                                                                                 end else begin
 618                                                                                         if (four_byte_address_mode) begin
 619                                                                                                 phy_tx_data <= spi_program_4ba_command_code;
 620                                                                                         end else begin
 621                                                                                                 phy_tx_data <= spi_program_3ba_command_code;
 622                                                                                         end
 623                                                                                 end
 624                                                                                 if (allow_multicycle_writes) begin
 625                                                                                         multicycle_write_in_progress <= 1;
 626                                                                                 end else begin
 627                                                                                         single_cycle_write_counter <= 0;
 628                                                                                 end
 629                                                                         end
 630                                                                         phy_qspi_mode_active <= 0;
 631                                                                         phy_qspi_transfer_mode <= 0;
 632                                                                         phy_dummy_cycle_count <= 0;
 633                                                                         phy_hold_ss_active <= 1;
 634                                                                         phy_cycle_start <= 1;
 635
 636                                                                         if (four_byte_address_mode) begin
 637                                                                                 multicycle_transaction_address <= spi_address_reg;
 638                                                                         end else begin
 639                                                                                 multicycle_transaction_address <= {8'h00, spi_address_reg[23:0]};
 640                                                                         end
 641
 642                                                                         spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_TR03;
 643                                                                 end
 644                                                         end
 645                                                 end
 646                                         end
 647
 648                                         if ((spi_cs_active_hold_cycles > 0) && (multicycle_read_in_progress || multicycle_write_in_progress)) begin
 649                                                 spi_cs_active_counter <= spi_cs_active_counter + 1;
 650                                         end else begin
 651                                                 spi_cs_active_counter <= 0;
 652                                         end
 653                                 end
 654                                 SPI_MASTER_TRANSFER_STATE_UC01: begin
 655                                         if (phy_transaction_complete) begin
 656                                                 phy_cycle_start <= 0;
 657
 658                                                 user_command_mode_read_during_write <= phy_rx_data[7:0];
 659                                                 if (!wishbone_data_cycle_type) begin
 660                                                         // Read cycle
 661                                                         // Replicate the output bytes to all active lanes
 662                                                         if (wishbone_sel_reg[0]) begin
 663                                                                 wishbone_dat_r_reg[31:24] <= phy_rx_data[7:0];
 664                                                         end
 665                                                         if (wishbone_sel_reg[1]) begin
 666                                                                 wishbone_dat_r_reg[23:16] <= phy_rx_data[7:0];
 667                                                         end
 668                                                         if (wishbone_sel_reg[2]) begin
 669                                                                 wishbone_dat_r_reg[15:8] <= phy_rx_data[7:0];
 670                                                         end
 671                                                         if (wishbone_sel_reg[3]) begin
 672                                                                 wishbone_dat_r_reg[7:0] <= phy_rx_data[7:0];
 673                                                         end
 674                                                 end
 675
 676                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_TR01;
 677                                         end
 678                                 end
 679                                 SPI_MASTER_TRANSFER_STATE_UC02: begin
 680                                         // Release CS and prepare the SPI device for the next command
 681                                         phy_hold_ss_active <= 0;
 682                                         phy_qspi_transfer_mode <= 0;
 683                                         phy_qspi_mode_active <= 0;
 684
 685                                         // Terminate user command mode / multicycle transfers
 686                                         user_command_mode_active <= 0;
 687                                         multicycle_read_in_progress <= 0;
 688                                         multicycle_write_in_progress <= 0;
 689                                         spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_UC03;
 690                                 end
 691                                 SPI_MASTER_TRANSFER_STATE_UC03: begin
 692                                         // Wait for CS to return to idle, since this state machine is running
 693                                         // significantly faster than the SPI PHY state machine.  This avoids
 694                                         // potentially short cycling the PHY and not allowing CS to return
 695                                         // to idle, thus inadvertently chaining the next command onto the
 696                                         // previous one!
 697                                         if (spi_ss_n) begin
 698                                                 if (cs_extra_idle_cycles > 0) begin
 699                                                         cs_extra_cycle_counter <= 1;
 700                                                         spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_UC04;
 701                                                 end else begin
 702                                                         // Return to idle
 703                                                         spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_IDLE;
 704                                                 end
 705                                         end
 706                                 end
 707                                 SPI_MASTER_TRANSFER_STATE_UC04: begin
 708                                         if (cs_extra_cycle_counter >= cs_extra_idle_cycles) begin
 709                                                 // Return to idle
 710                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_IDLE;
 711                                         end else begin
 712                                                 cs_extra_cycle_counter <= cs_extra_cycle_counter + 1;
 713                                         end
 714                                 end
 715                                 SPI_MASTER_TRANSFER_STATE_TR01: begin
 716                                         // Wait for CS to return to idle, since this state machine is running
 717                                         // significantly faster than the SPI PHY state machine.  This avoids
 718                                         // potentially short cycling the PHY and not allowing CS to return
 719                                         // to idle, thus inadvertently chaining the next command onto the
 720                                         // previous one!
 721                                         // If user command mode is active, CS will be asserted by design,
 722                                         // so ignore...
 723                                         if (spi_ss_n || user_command_mode_active
 724                                                 || multicycle_read_in_progress
 725                                                 || multicycle_write_in_progress) begin
 726                                                 if (!wishbone_data_cycle_type
 727                                                         && wishbone_access_is_32_bits
 728                                                         && !allow_multicycle_reads
 729                                                         && (single_cycle_read_counter < 4)) begin
 730                                                         // Set up SPI read access for next byte
 731                                                         if (phy_io_type == PHY_IO_TYPE_QUAD) begin
 732                                                                 if (four_byte_address_mode) begin
 733                                                                         if (fast_read_mode) begin
 734                                                                                 phy_tx_data <= qspi_fast_read_4ba_command_code;
 735                                                                         end else begin
 736                                                                                 phy_tx_data <= qspi_read_4ba_command_code;
 737                                                                         end
 738                                                                 end else begin
 739                                                                         if (fast_read_mode) begin
 740                                                                                 phy_tx_data <= qspi_fast_read_3ba_command_code;
 741                                                                         end else begin
 742                                                                                 phy_tx_data <= qspi_read_3ba_command_code;
 743                                                                         end
 744                                                                 end
 745                                                         end else begin
 746                                                                 if (four_byte_address_mode) begin
 747                                                                         if (fast_read_mode) begin
 748                                                                                 phy_tx_data <= spi_fast_read_4ba_command_code;
 749                                                                         end else begin
 750                                                                                 phy_tx_data <= spi_read_4ba_command_code;
 751                                                                         end
 752                                                                 end else begin
 753                                                                         if (fast_read_mode) begin
 754                                                                                 phy_tx_data <= spi_fast_read_3ba_command_code;
 755                                                                         end else begin
 756                                                                                 phy_tx_data <= spi_read_3ba_command_code;
 757                                                                         end
 758                                                                 end
 759                                                         end
 760
 761                                                         phy_qspi_mode_active <= 0;
 762                                                         phy_qspi_transfer_mode <= 0;
 763                                                         phy_dummy_cycle_count <= 0;
 764                                                         phy_hold_ss_active <= 1;
 765                                                         phy_cycle_start <= 1;
 766
 767                                                         spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_TR03;
 768                                                 end else if (wishbone_data_cycle_type
 769                                                         && wishbone_access_is_32_bits
 770                                                         && !allow_multicycle_writes
 771                                                         && (single_cycle_write_counter < 4)) begin
 772                                                         // Set up SPI write access for next byte
 773                                                         if (phy_io_type == PHY_IO_TYPE_QUAD) begin
 774                                                                 if (four_byte_address_mode) begin
 775                                                                         phy_tx_data <= qspi_program_4ba_command_code;
 776                                                                 end else begin
 777                                                                         phy_tx_data <= qspi_program_3ba_command_code;
 778                                                                 end
 779                                                         end else begin
 780                                                                 if (four_byte_address_mode) begin
 781                                                                         phy_tx_data <= spi_program_4ba_command_code;
 782                                                                 end else begin
 783                                                                         phy_tx_data <= spi_program_3ba_command_code;
 784                                                                 end
 785                                                         end
 786
 787                                                         phy_qspi_mode_active <= 0;
 788                                                         phy_qspi_transfer_mode <= 0;
 789                                                         phy_dummy_cycle_count <= 0;
 790                                                         phy_hold_ss_active <= 1;
 791                                                         phy_cycle_start <= 1;
 792
 793                                                         spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_TR03;
 794                                                 end else begin
 795                                                         // Signal transfer complete
 796                                                         wishbone_ack_reg <= 1;
 797
 798                                                         spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_TR02;
 799                                                 end
 800                                         end
 801                                 end
 802                                 SPI_MASTER_TRANSFER_STATE_TR02: begin
 803                                         // Cycle complete
 804                                         wishbone_ack_reg <= 0;
 805                                         spi_cs_active_counter <= 0;
 806                                         spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_IDLE;
 807                                 end
 808                                 SPI_MASTER_TRANSFER_STATE_TR03: begin
 809                                         if (phy_transaction_complete) begin
 810                                                 phy_cycle_start <= 0;
 811                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_TR04;
 812                                         end
 813                                 end
 814                                 SPI_MASTER_TRANSFER_STATE_TR04: begin
 815                                         if (phy_io_type_reg == PHY_IO_TYPE_QUAD) begin
 816                                                 if (!wishbone_data_cycle_type) begin
 817                                                         // Read
 818                                                         phy_qspi_mode_active <= qspi_read_quad_io_en;
 819                                                 end else begin
 820                                                         // Write
 821                                                         phy_qspi_mode_active <= qspi_write_quad_io_en;
 822                                                 end
 823                                         end else begin
 824                                                 phy_qspi_mode_active <= 0;
 825                                         end
 826                                         if (four_byte_address_mode) begin
 827                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_TR05;
 828                                         end else begin
 829                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_TR07;
 830                                         end
 831                                 end
 832                                 SPI_MASTER_TRANSFER_STATE_TR05: begin
 833                                         // Address (4 bytes / 1 word)
 834                                         if (!phy_transaction_complete) begin
 835                                                 if (wishbone_access_is_32_bits && !allow_multicycle_reads) begin
 836                                                         phy_tx_data <= multicycle_transaction_address;
 837                                                 end else begin
 838                                                         phy_tx_data <= spi_address_reg;
 839                                                 end
 840                                                 phy_qspi_transfer_mode <= 1;
 841                                                 phy_qspi_transfer_direction <= 1;
 842                                                 if (!wishbone_data_cycle_type) begin
 843                                                         // Read
 844                                                         if (fast_read_mode) begin
 845                                                                 phy_dummy_cycle_count <= dummy_cycle_count;
 846                                                         end else begin
 847                                                                 phy_dummy_cycle_count <= 0;
 848                                                         end
 849                                                 end else begin
 850                                                         // Write
 851                                                         phy_dummy_cycle_count <= 0;
 852                                                 end
 853                                                 phy_cycle_start <= 1;
 854
 855                                                 spi_byte_read_count <= 0;
 856                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_TR06;
 857                                         end
 858                                 end
 859                                 SPI_MASTER_TRANSFER_STATE_TR06: begin
 860                                         if (phy_transaction_complete) begin
 861                                                 phy_cycle_start <= 0;
 862
 863                                                 if (phy_io_type_reg == PHY_IO_TYPE_QUAD) begin
 864                                                         phy_qspi_mode_active <= 1;
 865                                                 end else begin
 866                                                         phy_qspi_mode_active <= 0;
 867                                                 end
 868
 869                                                 if (wishbone_data_cycle_type) begin
 870                                                         spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_WR01;
 871                                                 end else begin
 872                                                         spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_RD01;
 873                                                 end
 874                                         end
 875                                 end
 876                                 SPI_MASTER_TRANSFER_STATE_RD01: begin
 877                                         if (!phy_transaction_complete) begin
 878                                                 // Data words
 879                                                 phy_tx_data <= 0;       // Not used
 880                                                 if (phy_io_type_reg == PHY_IO_TYPE_QUAD) begin
 881                                                         phy_qspi_mode_active <= 1;
 882                                                 end else begin
 883                                                         phy_qspi_mode_active <= 0;
 884                                                 end
 885                                                 if (wishbone_access_is_32_bits && allow_multicycle_reads) begin
 886                                                         phy_qspi_transfer_mode <= 1;
 887                                                 end else begin
 888                                                         phy_qspi_transfer_mode <= 0;
 889                                                 end
 890                                                 phy_qspi_transfer_direction <= 0;
 891                                                 phy_dummy_cycle_count <= 0;
 892                                                 phy_cycle_start <= 1;
 893                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_RD02;
 894                                         end
 895                                 end
 896                                 SPI_MASTER_TRANSFER_STATE_RD02: begin
 897                                         if (phy_transaction_complete) begin
 898                                                 // Set Wishbone output data
 899                                                 if (wishbone_access_is_32_bits) begin
 900                                                         if (allow_multicycle_reads) begin
 901                                                                 wishbone_dat_r_reg <= phy_rx_data;
 902                                                                 multicycle_transaction_address <= multicycle_transaction_address + 4;
 903                                                         end else begin
 904                                                                 if (single_cycle_read_counter == 0) begin
 905                                                                         wishbone_dat_r_reg[31:24] <= phy_rx_data[7:0];
 906                                                                 end else if (single_cycle_read_counter == 1) begin
 907                                                                         wishbone_dat_r_reg[23:16] <= phy_rx_data[7:0];
 908                                                                 end else if (single_cycle_read_counter == 2) begin
 909                                                                         wishbone_dat_r_reg[15:8] <= phy_rx_data[7:0];
 910                                                                 end else if (single_cycle_read_counter == 3) begin
 911                                                                         wishbone_dat_r_reg[7:0] <= phy_rx_data[7:0];
 912                                                                 end
 913                                                                 single_cycle_read_counter <= single_cycle_read_counter + 1;
 914                                                                 multicycle_transaction_address <= multicycle_transaction_address + 1;
 915                                                         end
 916                                                 end else begin
 917                                                         // Replicate the data bytes to all active lanes
 918                                                         if (wishbone_sel_reg[0]) begin
 919                                                                 wishbone_dat_r_reg[31:24] <= phy_rx_data[7:0];
 920                                                         end
 921                                                         if (wishbone_sel_reg[1]) begin
 922                                                                 wishbone_dat_r_reg[23:16] <= phy_rx_data[7:0];
 923                                                         end
 924                                                         if (wishbone_sel_reg[2]) begin
 925                                                                 wishbone_dat_r_reg[15:8] <= phy_rx_data[7:0];
 926                                                         end
 927                                                         if (wishbone_sel_reg[3]) begin
 928                                                                 wishbone_dat_r_reg[7:0] <= phy_rx_data[7:0];
 929                                                         end
 930                                                         multicycle_transaction_address <= multicycle_transaction_address + 1;
 931                                                 end
 932
 933                                                 phy_cycle_start <= 0;
 934                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_RD03;
 935                                         end
 936                                 end
 937                                 SPI_MASTER_TRANSFER_STATE_RD03: begin
 938                                         if (!phy_transaction_complete) begin
 939                                                 // Release CS (if required)
 940                                                 if (!multicycle_read_in_progress) begin
 941                                                         phy_hold_ss_active <= 0;
 942                                                 end
 943
 944                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_TR01;
 945                                         end
 946                                 end
 947                                 SPI_MASTER_TRANSFER_STATE_WR01: begin
 948                                         if (!phy_transaction_complete) begin
 949                                                 // Data words
 950                                                 if (wishbone_access_is_32_bits) begin
 951                                                         if (allow_multicycle_writes) begin
 952                                                                 phy_tx_data <= wishbone_dat_w;
 953                                                                 phy_qspi_transfer_mode <= 1;
 954                                                                 multicycle_transaction_address <= multicycle_transaction_address + 4;
 955                                                         end else begin
 956                                                                 if (single_cycle_write_counter == 0) begin
 957                                                                         phy_tx_data[7:0] <= wishbone_dat_w[7:0];
 958                                                                 end else if (single_cycle_write_counter == 1) begin
 959                                                                         phy_tx_data[7:0] <= wishbone_dat_w[15:8];
 960                                                                 end else if (single_cycle_write_counter == 2) begin
 961                                                                         phy_tx_data[7:0] <= wishbone_dat_w[23:16];
 962                                                                 end else if (single_cycle_write_counter == 3) begin
 963                                                                         phy_tx_data[7:0] <= wishbone_dat_w[31:24];
 964                                                                 end
 965                                                                 phy_qspi_transfer_mode <= 0;
 966                                                                 single_cycle_write_counter <= single_cycle_write_counter + 1;
 967                                                                 multicycle_transaction_address <= multicycle_transaction_address + 1;
 968                                                         end
 969                                                 end else begin
 970                                                         // Write cycle
 971                                                         // Read the data byte to write from the active lane
 972                                                         if (wishbone_sel_reg[0]) begin
 973                                                                 phy_tx_data[7:0] <= wishbone_dat_w[31:24];
 974                                                         end else if (wishbone_sel_reg[1]) begin
 975                                                                 phy_tx_data[7:0] <= wishbone_dat_w[23:16];
 976                                                         end else if (wishbone_sel_reg[2]) begin
 977                                                                 phy_tx_data[7:0] <= wishbone_dat_w[15:8];
 978                                                         end else if (wishbone_sel_reg[3]) begin
 979                                                                 phy_tx_data[7:0] <= wishbone_dat_w[7:0];
 980                                                         end else begin
 981                                                                 phy_tx_data[7:0] = 8'hff;       // Safe default -- will not overwrite any bits
 982                                                         end
 983                                                         phy_tx_data[31:8] = 0;
 984                                                         phy_qspi_transfer_mode <= 0;
 985                                                         multicycle_transaction_address <= multicycle_transaction_address + 1;
 986                                                 end
 987                                                 if (phy_io_type_reg == PHY_IO_TYPE_QUAD) begin
 988                                                         phy_qspi_mode_active <= 1;
 989                                                 end else begin
 990                                                         phy_qspi_mode_active <= 0;
 991                                                 end
 992                                                 phy_qspi_transfer_direction <= 1;
 993                                                 phy_dummy_cycle_count <= 0;
 994                                                 phy_cycle_start <= 1;
 995                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_WR02;
 996                                         end
 997                                 end
 998                                 SPI_MASTER_TRANSFER_STATE_WR02: begin
 999                                         if (phy_transaction_complete) begin
1000                                                 phy_cycle_start <= 0;
1001
1002                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_WR03;
1003                                         end
1004                                 end
1005                                 SPI_MASTER_TRANSFER_STATE_WR03: begin
1006                                         if (!phy_transaction_complete) begin
1007                                                 // Release CS (if required)
1008                                                 if (!multicycle_write_in_progress) begin
1009                                                         phy_hold_ss_active <= 0;
1010                                                 end
1011
1012                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_TR01;
1013                                         end
1014                                 end
1015                                 SPI_MASTER_TRANSFER_STATE_TR07: begin
1016                                         // Send the three address bytes one at a time...
1017                                         if (!phy_transaction_complete) begin
1018                                                 if (wishbone_access_is_32_bits && !allow_multicycle_reads) begin
1019                                                         phy_tx_data <= multicycle_transaction_address[23:16];
1020                                                 end else begin
1021                                                         phy_tx_data <= spi_address_reg[23:16];
1022                                                 end
1023                                                 if (phy_io_type_reg == PHY_IO_TYPE_QUAD) begin
1024                                                         phy_qspi_mode_active <= 1;
1025                                                 end else begin
1026                                                         phy_qspi_mode_active <= 0;
1027                                                 end
1028                                                 phy_qspi_transfer_mode <= 0;
1029                                                 phy_qspi_transfer_direction <= 1;
1030                                                 phy_dummy_cycle_count <= 0;
1031                                                 phy_cycle_start <= 1;
1032
1033                                                 spi_byte_read_count <= 0;
1034                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_TR08;
1035                                         end
1036                                 end
1037                                 SPI_MASTER_TRANSFER_STATE_TR08: begin
1038                                         if (phy_transaction_complete) begin
1039                                                 phy_cycle_start <= 0;
1040                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_TR09;
1041                                         end
1042                                 end
1043                                 SPI_MASTER_TRANSFER_STATE_TR09: begin
1044                                         if (!phy_transaction_complete) begin
1045                                                 if (wishbone_access_is_32_bits && !allow_multicycle_reads) begin
1046                                                         phy_tx_data <= multicycle_transaction_address[15:8];
1047                                                 end else begin
1048                                                         phy_tx_data <= spi_address_reg[15:8];
1049                                                 end
1050                                                 if (phy_io_type_reg == PHY_IO_TYPE_QUAD) begin
1051                                                         phy_qspi_mode_active <= 1;
1052                                                 end else begin
1053                                                         phy_qspi_mode_active <= 0;
1054                                                 end
1055                                                 phy_qspi_transfer_mode <= 0;
1056                                                 phy_qspi_transfer_direction <= 1;
1057                                                 phy_dummy_cycle_count <= 0;
1058                                                 phy_cycle_start <= 1;
1059
1060                                                 spi_byte_read_count <= 0;
1061                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_TR10;
1062                                         end
1063                                 end
1064                                 SPI_MASTER_TRANSFER_STATE_TR10: begin
1065                                         if (phy_transaction_complete) begin
1066                                                 phy_cycle_start <= 0;
1067                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_TR11;
1068                                         end
1069                                 end
1070                                 SPI_MASTER_TRANSFER_STATE_TR11: begin
1071                                         if (!phy_transaction_complete) begin
1072                                                 if (wishbone_access_is_32_bits && !allow_multicycle_reads) begin
1073                                                         phy_tx_data <= multicycle_transaction_address[7:0];
1074                                                 end else begin
1075                                                         phy_tx_data <= spi_address_reg[7:0];
1076                                                 end
1077                                                 if (phy_io_type_reg == PHY_IO_TYPE_QUAD) begin
1078                                                         phy_qspi_mode_active <= 1;
1079                                                 end else begin
1080                                                         phy_qspi_mode_active <= 0;
1081                                                 end
1082                                                 phy_qspi_transfer_mode <= 0;
1083                                                 phy_qspi_transfer_direction <= 1;
1084                                                 if (!wishbone_data_cycle_type) begin
1085                                                         // Read
1086                                                         if (fast_read_mode) begin
1087                                                                 phy_dummy_cycle_count <= dummy_cycle_count;
1088                                                         end else begin
1089                                                                 phy_dummy_cycle_count <= 0;
1090                                                         end
1091                                                 end else begin
1092                                                         phy_dummy_cycle_count <= 0;
1093                                                 end
1094                                                 phy_cycle_start <= 1;
1095
1096                                                 spi_byte_read_count <= 0;
1097                                                 spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_TR12;
1098                                         end
1099                                 end
1100                                 SPI_MASTER_TRANSFER_STATE_TR12: begin
1101                                         if (phy_transaction_complete) begin
1102                                                 phy_cycle_start <= 0;
1103                                                 if (wishbone_data_cycle_type) begin
1104                                                         spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_WR01;
1105                                                 end else begin
1106                                                         spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_RD01;
1107                                                 end
1108                                         end
1109                                 end
1110                                 default: begin
1111                                         spi_transfer_state <= SPI_MASTER_TRANSFER_STATE_IDLE;
1112                                 end
1113                         endcase
1114                 end
1115         end
1116 endmodule