versa_ecp5.py

   1 #!/usr/bin/env python3
   2
   3 import os
   4 import argparse
   5
   6 import litex_boards.targets.versa_ecp5 as versa_ecp5
   7 import litex_boards.targets.ulx3s as ulx3s
   8
   9 from litex.soc.integration.soc_sdram import (soc_sdram_args,
  10                                              soc_sdram_argdict)
  11 from litex.soc.integration.builder import (Builder, builder_args,
  12                                            builder_argdict)
  13
  14 from libresoc import LibreSoC
  15 #from microwatt import Microwatt
  16
  17 # HACK!
  18 from litex.soc.integration.soc import SoCCSRHandler
  19 SoCCSRHandler.supported_address_width.append(12)
  20
  21
  22 # TestSoC
  23 # ----------------------------------------------------------------------------
  24
  25 from litex.build.generic_platform import Subsignal, Pins, IOStandard
  26
  27 class VersaECP5TestSoC(versa_ecp5.BaseSoC):
  28     def __init__(self, sys_clk_freq=int(16e6), **kwargs):
  29         kwargs["integrated_rom_size"] = 0x10000
  30         #kwargs["integrated_main_ram_size"] = 0x1000
  31         kwargs["csr_data_width"] = 32
  32         kwargs['csr_address_width'] = 12 # limit to 0x8000
  33         kwargs["l2_size"] = 0
  34         #bus_data_width = 16,
  35
  36         versa_ecp5.BaseSoC.__init__(self,
  37             sys_clk_freq = sys_clk_freq,
  38             cpu_type     = "external",
  39             cpu_cls      = LibreSoC,
  40             cpu_variant = "standardjtagnoirq",
  41             #cpu_cls      = Microwatt,
  42             device       = "LFE5UM",
  43             **kwargs)
  44
  45         # (thanks to daveshah for this tip)
  46         # use platform.add_extension to first define the pins
  47         # https://github.com/daveshah1/linux-on-litex-vexriscv/commit/dc97bac3aeb04cfbf5116a6c7e324ce849391770#diff-2353956cb1116676bd6b96769c8ebf7b4b86c16c47511eb2888d0dd2a979e09eR117-R134
  48
  49         # define the pins, add as an extension, *then* request it
  50         jtag_ios = [
  51             ("jtag", 0,
  52                 Subsignal("tdi", Pins("B19"), IOStandard("LVCMOS33")),
  53                 Subsignal("tms", Pins("B12"), IOStandard("LVCMOS33")),
  54                 Subsignal("tck", Pins("B9"), IOStandard("LVCMOS33")),
  55                 Subsignal("tdo", Pins("E6"), IOStandard("LVCMOS33")),
  56             )
  57         ]
  58         self.platform.add_extension(jtag_ios)
  59         jtag = self.platform.request("jtag")
  60
  61         # wire the pins up to CPU JTAG
  62         self.comb += self.cpu.jtag_tck.eq(jtag.tck)
  63         self.comb += self.cpu.jtag_tms.eq(jtag.tms)
  64         self.comb += self.cpu.jtag_tdi.eq(jtag.tdi)
  65         self.comb += jtag.tdo.eq(self.cpu.jtag_tdo)
  66
  67
  68         #self.add_constant("MEMTEST_BUS_SIZE",  256//16)
  69         #self.add_constant("MEMTEST_DATA_SIZE", 256//16)
  70         #self.add_constant("MEMTEST_ADDR_SIZE", 256//16)
  71
  72         #self.add_constant("MEMTEST_BUS_DEBUG", 1)
  73         #self.add_constant("MEMTEST_ADDR_DEBUG", 1)
  74         #self.add_constant("MEMTEST_DATA_DEBUG", 1)
  75
  76
  77 class ULX3S85FTestSoC(ulx3s.BaseSoC):
  78     def __init__(self, sys_clk_freq=int(16e6), **kwargs):
  79         kwargs["integrated_rom_size"] = 0x10000
  80         #kwargs["integrated_main_ram_size"] = 0x1000
  81         kwargs["csr_data_width"] = 32
  82         kwargs["l2_size"] = 0
  83         #bus_data_width = 16,
  84
  85         ulx3s.BaseSoC.__init__(self,
  86             sys_clk_freq = sys_clk_freq,
  87             cpu_type     = "external",
  88             cpu_cls      = LibreSoC,
  89             cpu_variant  = "standardjtag",
  90             #cpu_cls      = Microwatt,
  91             device       = "LFE5U-85F",
  92             **kwargs)
  93
  94         # get 4 arbitrarily assinged logical pins, each gpio has
  95         # 2 distinct physical single non-differential pins p and n
  96         gpio0    = self.platform.request("gpio", 0)
  97         gpio1    = self.platform.request("gpio", 1)
  98
  99         # assign p, n litex 'subsignals' of each gpio to jtag pins
 100         jtag_tdi = gpio0.n
 101         jtag_tms = gpio0.p
 102         jtag_tck = gpio1.n
 103         jtag_tdo = gpio1.p
 104
 105         # wire the pins up to CPU JTAG
 106         self.comb += self.cpu.jtag_tdi.eq(jtag_tdi)
 107         self.comb += self.cpu.jtag_tms.eq(jtag_tms)
 108         self.comb += self.cpu.jtag_tdi.eq(jtag_tdi)
 109         self.comb += jtag_tdo.eq(self.cpu.jtag_tdo)
 110
 111 # Build
 112 # ----------------------------------------------------------------------------
 113
 114 def main():
 115     parser = argparse.ArgumentParser(description="LiteX SoC with LibreSoC " \
 116                                      "CPU on Versa ECP5 or ULX3S LFE5U85F")
 117     parser.add_argument("--build", action="store_true", help="Build bitstream")
 118     parser.add_argument("--load", action="store_true", help="Load bitstream")
 119     parser.add_argument("--sys-clk-freq",  default=int(16e6),
 120                         help="System clock frequency (default=16MHz)")
 121     parser.add_argument("--fpga", default="versa_ecp5", help="FPGA target " \
 122                         "to build for/load to")
 123
 124     builder_args(parser)
 125     soc_sdram_args(parser)
 126     args = parser.parse_args()
 127
 128     if args.fpga == "versa_ecp5":
 129         soc = VersaECP5TestSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
 130                                **soc_sdram_argdict(args))
 131
 132     elif args.fpga == "ulx3s85f":
 133         soc = ULX3S85FTestSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
 134                               **soc_sdram_argdict(args))
 135
 136     else:
 137         soc = VersaECP5TestSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
 138                                **soc_sdram_argdict(args))
 139
 140     builder = Builder(soc, **builder_argdict(args))
 141     builder.build(run=args.build)
 142
 143     if args.load:
 144         prog = soc.platform.create_programmer()
 145         prog.load_bitstream(os.path.join(builder.gateware_dir,
 146                                          soc.build_name + ".svf"))
 147
 148 if __name__ == "__main__":
 149     main()