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remove extra arg from old roundz function
[ieee754fpu.git]
/
src
/
add
/
fpbase.py
diff --git
a/src/add/fpbase.py
b/src/add/fpbase.py
index 7f4f2cc88d57813c22d70f31837290fcd2753e7e..db95eb13e2a4ef7ae7199c6a29e05865674fc62a 100644
(file)
--- a/
src/add/fpbase.py
+++ b/
src/add/fpbase.py
@@
-398,7
+398,7
@@
class Trigger:
def elaborate(self, platform):
m = Module()
def elaborate(self, platform):
m = Module()
- m.d.
sync
+= self.trigger.eq(self.stb & self.ack)
+ m.d.
comb
+= self.trigger.eq(self.stb & self.ack)
return m
def copy(self, inp):
return m
def copy(self, inp):
@@
-558,14
+558,13
@@
class FPBase:
with m.Else():
m.next = next_state
with m.Else():
m.next = next_state
- def roundz(self, m, z,
out_z,
roundz):
+ def roundz(self, m, z, roundz):
""" performs rounding on the output. TODO: different kinds of rounding
"""
""" performs rounding on the output. TODO: different kinds of rounding
"""
- m.d.comb += out_z.copy(z) # copies input to output first
with m.If(roundz):
with m.If(roundz):
- m.d.
comb += out_
z.m.eq(z.m + 1) # mantissa rounds up
+ m.d.
sync +=
z.m.eq(z.m + 1) # mantissa rounds up
with m.If(z.m == z.m1s): # all 1s
with m.If(z.m == z.m1s): # all 1s
- m.d.
comb += out_
z.e.eq(z.e + 1) # exponent rounds up
+ m.d.
sync +=
z.e.eq(z.e + 1) # exponent rounds up
def corrections(self, m, z, next_state):
""" denormalisation and sign-bug corrections
def corrections(self, m, z, next_state):
""" denormalisation and sign-bug corrections