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remove extra arg from old roundz function
[ieee754fpu.git]
/
src
/
add
/
fpbase.py
diff --git
a/src/add/fpbase.py
b/src/add/fpbase.py
index d6a059e0339b0ea4c7464a2274a1e474cecb1535..db95eb13e2a4ef7ae7199c6a29e05865674fc62a 100644
(file)
--- a/
src/add/fpbase.py
+++ b/
src/add/fpbase.py
@@
-188,11
+188,13
@@
class MultiShiftRMerge:
""" shifts down (right) and merges lower bits into m[0].
m[0] is the "sticky" bit, basically
"""
""" shifts down (right) and merges lower bits into m[0].
m[0] is the "sticky" bit, basically
"""
- def __init__(self, width):
- self.smax = int(log(width) / log(2))
+ def __init__(self, width, s_max=None):
+ if s_max is None:
+ s_max = int(log(width) / log(2))
+ self.smax = s_max
self.m = Signal(width, reset_less=True)
self.inp = Signal(width, reset_less=True)
self.m = Signal(width, reset_less=True)
self.inp = Signal(width, reset_less=True)
- self.diff = Signal(s
elf.s
max, reset_less=True)
+ self.diff = Signal(s
_
max, reset_less=True)
self.width = width
def elaborate(self, platform):
self.width = width
def elaborate(self, platform):
@@
-202,12
+204,16
@@
class MultiShiftRMerge:
m_mask = Signal(self.width, reset_less=True)
smask = Signal(self.width, reset_less=True)
stickybit = Signal(reset_less=True)
m_mask = Signal(self.width, reset_less=True)
smask = Signal(self.width, reset_less=True)
stickybit = Signal(reset_less=True)
+ maxslen = Signal(self.smax, reset_less=True)
+ maxsleni = Signal(self.smax, reset_less=True)
sm = MultiShift(self.width-1)
m0s = Const(0, self.width-1)
mw = Const(self.width-1, len(self.diff))
sm = MultiShift(self.width-1)
m0s = Const(0, self.width-1)
mw = Const(self.width-1, len(self.diff))
- maxslen = Mux(self.diff > mw, mw, self.diff)
- maxsleni = mw - maxslen
+ m.d.comb += [maxslen.eq(Mux(self.diff > mw, mw, self.diff)),
+ maxsleni.eq(Mux(self.diff > mw, 0, mw-self.diff)),
+ ]
+
m.d.comb += [
# shift mantissa by maxslen, mask by inverse
rs.eq(sm.rshift(self.inp[1:], maxslen)),
m.d.comb += [
# shift mantissa by maxslen, mask by inverse
rs.eq(sm.rshift(self.inp[1:], maxslen)),
@@
-366,10
+372,10
@@
class FPNumIn(FPNumBase):
maxsleni = mw - maxslen
m_mask = sm.rshift(self.m1s[1:], maxsleni) # shift and invert
maxsleni = mw - maxslen
m_mask = sm.rshift(self.m1s[1:], maxsleni) # shift and invert
- #stickybit
s
= reduce(or_, inp.m[1:] & m_mask) | inp.m[0]
- stickybit
s
= (inp.m[1:] & m_mask).bool() | inp.m[0]
+ #stickybit = reduce(or_, inp.m[1:] & m_mask) | inp.m[0]
+ stickybit = (inp.m[1:] & m_mask).bool() | inp.m[0]
return [self.e.eq(inp.e + diff),
return [self.e.eq(inp.e + diff),
- self.m.eq(Cat(stickybit
s
, rs))
+ self.m.eq(Cat(stickybit, rs))
]
def shift_up_multi(self, diff):
]
def shift_up_multi(self, diff):
@@
-383,20
+389,34
@@
class FPNumIn(FPNumBase):
self.m.eq(sm.lshift(self.m, maxslen))
]
self.m.eq(sm.lshift(self.m, maxslen))
]
-class FPOp:
- def __init__(self, width):
- self.width = width
+class Trigger:
+ def __init__(self):
- self.v = Signal(width)
self.stb = Signal(reset=0)
self.ack = Signal()
self.trigger = Signal(reset_less=True)
def elaborate(self, platform):
m = Module()
self.stb = Signal(reset=0)
self.ack = Signal()
self.trigger = Signal(reset_less=True)
def elaborate(self, platform):
m = Module()
- m.d.
sync
+= self.trigger.eq(self.stb & self.ack)
+ m.d.
comb
+= self.trigger.eq(self.stb & self.ack)
return m
return m
+ def copy(self, inp):
+ return [self.stb.eq(inp.stb),
+ self.ack.eq(inp.ack)
+ ]
+
+ def ports(self):
+ return [self.stb, self.ack]
+
+
+class FPOp(Trigger):
+ def __init__(self, width):
+ Trigger.__init__(self)
+ self.width = width
+
+ self.v = Signal(width)
+
def chain_inv(self, in_op, extra=None):
stb = in_op.stb
if extra is not None:
def chain_inv(self, in_op, extra=None):
stb = in_op.stb
if extra is not None:
@@
-538,14
+558,13
@@
class FPBase:
with m.Else():
m.next = next_state
with m.Else():
m.next = next_state
- def roundz(self, m, z,
out_z,
roundz):
+ def roundz(self, m, z, roundz):
""" performs rounding on the output. TODO: different kinds of rounding
"""
""" performs rounding on the output. TODO: different kinds of rounding
"""
- m.d.comb += out_z.copy(z) # copies input to output first
with m.If(roundz):
with m.If(roundz):
- m.d.
comb += out_
z.m.eq(z.m + 1) # mantissa rounds up
+ m.d.
sync +=
z.m.eq(z.m + 1) # mantissa rounds up
with m.If(z.m == z.m1s): # all 1s
with m.If(z.m == z.m1s): # all 1s
- m.d.
comb += out_
z.e.eq(z.e + 1) # exponent rounds up
+ m.d.
sync +=
z.e.eq(z.e + 1) # exponent rounds up
def corrections(self, m, z, next_state):
""" denormalisation and sign-bug corrections
def corrections(self, m, z, next_state):
""" denormalisation and sign-bug corrections