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sifive-blocks: trust diplomacy to get names right
[sifive-blocks.git]
/
src
/
main
/
scala
/
devices
/
spi
/
SPIPeriphery.scala
diff --git
a/src/main/scala/devices/spi/SPIPeriphery.scala
b/src/main/scala/devices/spi/SPIPeriphery.scala
index 40bcec692f9265f5b9fa590a09a060194244ff23..f4773a228c7cabf9646381ed4b9cea756be77270 100644
(file)
--- a/
src/main/scala/devices/spi/SPIPeriphery.scala
+++ b/
src/main/scala/devices/spi/SPIPeriphery.scala
@@
-8,8
+8,8
@@
import rocketchip.{TopNetwork,TopNetworkModule}
trait PeripherySPI {
this: TopNetwork { val spiConfigs: Seq[SPIConfig] } =>
trait PeripherySPI {
this: TopNetwork { val spiConfigs: Seq[SPIConfig] } =>
- val spi
Devices
= (spiConfigs.zipWithIndex) map {case (c, i) =>
- val spi = LazyModule(new TLSPI(c)
{ override lazy val valName = Some(s"spi$i") }
)
+ val spi = (spiConfigs.zipWithIndex) map {case (c, i) =>
+ val spi = LazyModule(new TLSPI(c))
spi.rnode := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
intBus.intnode := spi.intnode
spi
spi.rnode := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
intBus.intnode := spi.intnode
spi
@@
-28,7
+28,7
@@
trait PeripherySPIModule {
val outer: PeripherySPI
val io: PeripherySPIBundle
} =>
val outer: PeripherySPI
val io: PeripherySPIBundle
} =>
- (io.spis zip outer.spi
Devices
).foreach { case (io, device) =>
+ (io.spis zip outer.spi).foreach { case (io, device) =>
io <> device.module.io.port
}
}
io <> device.module.io.port
}
}