trait PeripheryPWM {
this: TopNetwork { val pwmConfigs: Seq[PWMConfig] } =>
- val pwmDevices = (pwmConfigs.zipWithIndex) map { case (c, i) =>
- val pwm = LazyModule(new TLPWM(c) { override lazy val valName = Some(s"pwm$i") })
+ val pwm = (pwmConfigs.zipWithIndex) map { case (c, i) =>
+ val pwm = LazyModule(new TLPWM(c))
pwm.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
intBus.intnode := pwm.intnode
pwm
val outer: PeripheryPWM
val io: PeripheryPWMBundle
} =>
- (io.pwms.zipWithIndex zip outer.pwmDevices) foreach { case ((io, i), device) =>
+ (io.pwms.zipWithIndex zip outer.pwm) foreach { case ((io, i), device) =>
io.port := device.module.io.gpio
}
}
trait PeripherySPI {
this: TopNetwork { val spiConfigs: Seq[SPIConfig] } =>
- val spiDevices = (spiConfigs.zipWithIndex) map {case (c, i) =>
- val spi = LazyModule(new TLSPI(c) { override lazy val valName = Some(s"spi$i") } )
+ val spi = (spiConfigs.zipWithIndex) map {case (c, i) =>
+ val spi = LazyModule(new TLSPI(c))
spi.rnode := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
intBus.intnode := spi.intnode
spi
val outer: PeripherySPI
val io: PeripherySPIBundle
} =>
- (io.spis zip outer.spiDevices).foreach { case (io, device) =>
+ (io.spis zip outer.spi).foreach { case (io, device) =>
io <> device.module.io.port
}
}
this: TopNetwork {
val uartConfigs: Seq[UARTConfig]
} =>
- val uartDevices = uartConfigs.zipWithIndex.map { case (c, i) =>
- val uart = LazyModule(new UART(c) { override lazy val valName = Some(s"uart$i") } )
+ val uart = uartConfigs.zipWithIndex.map { case (c, i) =>
+ val uart = LazyModule(new UART(c))
uart.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
intBus.intnode := uart.intnode
uart
val outer: PeripheryUART
val io: PeripheryUARTBundle
} =>
- (io.uarts zip outer.uartDevices).foreach { case (io, device) =>
+ (io.uarts zip outer.uart).foreach { case (io, device) =>
io <> device.module.io.port
}
}