projects
/
sifive-blocks.git
/ blobdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
|
commitdiff
|
tree
raw
|
inline
| side by side
sifive-blocks: trust diplomacy to get names right
[sifive-blocks.git]
/
src
/
main
/
scala
/
devices
/
uart
/
UARTPeriphery.scala
diff --git
a/src/main/scala/devices/uart/UARTPeriphery.scala
b/src/main/scala/devices/uart/UARTPeriphery.scala
index fd5bc35db4838105187197ef82622c31c948a2d1..3639d9baebef5c5ad1e5541e62f1a9e679ae52aa 100644
(file)
--- a/
src/main/scala/devices/uart/UARTPeriphery.scala
+++ b/
src/main/scala/devices/uart/UARTPeriphery.scala
@@
-14,8
+14,8
@@
trait PeripheryUART {
this: TopNetwork {
val uartConfigs: Seq[UARTConfig]
} =>
this: TopNetwork {
val uartConfigs: Seq[UARTConfig]
} =>
- val uart
Devices
= uartConfigs.zipWithIndex.map { case (c, i) =>
- val uart = LazyModule(new UART(c)
{ override lazy val valName = Some(s"uart$i") }
)
+ val uart = uartConfigs.zipWithIndex.map { case (c, i) =>
+ val uart = LazyModule(new UART(c))
uart.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
intBus.intnode := uart.intnode
uart
uart.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
intBus.intnode := uart.intnode
uart
@@
-32,7
+32,7
@@
trait PeripheryUARTModule {
val outer: PeripheryUART
val io: PeripheryUARTBundle
} =>
val outer: PeripheryUART
val io: PeripheryUARTBundle
} =>
- (io.uarts zip outer.uart
Devices
).foreach { case (io, device) =>
+ (io.uarts zip outer.uart).foreach { case (io, device) =>
io <> device.module.io.port
}
}
io <> device.module.io.port
}
}