-import config._
-import diplomacy._
-import uncore.tilelink2._
-import rocketchip._
-
-import sifive.blocks.devices.gpio.{GPIOPin, GPIOOutputPinCtrl, GPIOInputPinCtrl}
-import sifive.blocks.util.ShiftRegisterInit
-
-trait PeripheryUART {
- this: TopNetwork {
- val uartConfigs: Seq[UARTConfig]
- } =>
- val uart = uartConfigs.zipWithIndex.map { case (c, i) =>
- val uart = LazyModule(new UART(c))
- uart.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
- intBus.intnode := uart.intnode
+import chisel3.experimental.{withClockAndReset}
+import freechips.rocketchip.config.Field
+import freechips.rocketchip.util.SyncResetSynchronizerShiftReg
+import freechips.rocketchip.coreplex.{HasPeripheryBus, PeripheryBusParams, HasInterruptBus}
+import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
+import sifive.blocks.devices.pinctrl.{Pin}
+
+case object PeripheryUARTKey extends Field[Seq[UARTParams]]
+
+trait HasPeripheryUART extends HasPeripheryBus with HasInterruptBus {
+ private val divinit = (p(PeripheryBusParams).frequency / 115200).toInt
+ val uartParams = p(PeripheryUARTKey).map(_.copy(divisorInit = divinit))
+ val uarts = uartParams map { params =>
+ val uart = LazyModule(new TLUART(pbus.beatBytes, params))
+ uart.node := pbus.toVariableWidthSlaves
+ ibus.fromSync := uart.intnode