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shiftregs: Use SyncResetSynchronizerShiftReg primitives where appropriate synchronizers
[sifive-blocks.git] / src / main / scala / devices / uart /
drwxr-xr-x   ..
-rw-r--r-- 7449 UART.scala blob | history | raw
-rw-r--r-- 277 UARTCtrlRegs.scala blob | history | raw
-rw-r--r-- 1881 UARTPeriphery.scala blob | history | raw
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