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axi4: switch to new pipelined converters
[sifive-blocks.git]
/
src
/
main
/
scala
/
devices
/
xilinxvc707mig
/
XilinxVC707MIG.scala
diff --git
a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala
b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala
index 526305a4e6ce42dcbbaedec436defae87d5f09ac..c248f6c5553b05f317aee6bbd285bc81c7719e9f 100644
(file)
--- a/
src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala
+++ b/
src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala
@@
-2,28
+2,21
@@
package sifive.blocks.devices.xilinxvc707mig
import Chisel._
package sifive.blocks.devices.xilinxvc707mig
import Chisel._
+import chisel3.experimental.{Analog,attach}
import config._
import diplomacy._
import uncore.tilelink2._
import uncore.axi4._
import rocketchip._
import config._
import diplomacy._
import uncore.tilelink2._
import uncore.axi4._
import rocketchip._
-import sifive.blocks.ip.xilinx.vc707mig.{VC707MIG
UnidirectionalIOClocksReset, VC707MIGUnidirectional
IODDR, vc707mig}
+import sifive.blocks.ip.xilinx.vc707mig.{VC707MIG
IOClocksReset, VC707MIG
IODDR, vc707mig}
trait HasXilinxVC707MIGParameters {
}
trait HasXilinxVC707MIGParameters {
}
-class XilinxVC707MIGPads extends Bundle with VC707MIGUnidirectionalIODDR {
- val _inout_ddr3_dq = Bits(OUTPUT,64)
- val _inout_ddr3_dqs_n = Bits(OUTPUT,8)
- val _inout_ddr3_dqs_p = Bits(OUTPUT,8)
-}
+class XilinxVC707MIGPads extends Bundle with VC707MIGIODDR
-class XilinxVC707MIGIO extends Bundle with VC707MIGUnidirectionalIODDR
- with VC707MIGUnidirectionalIOClocksReset {
- val _inout_ddr3_dq = Bits(OUTPUT,64)
- val _inout_ddr3_dqs_n = Bits(OUTPUT,8)
- val _inout_ddr3_dqs_p = Bits(OUTPUT,8)
-}
+class XilinxVC707MIGIO extends Bundle with VC707MIGIODDR
+ with VC707MIGIOClocksReset
class XilinxVC707MIG(implicit p: Parameters) extends LazyModule with HasXilinxVC707MIGParameters {
val device = new MemoryDevice
class XilinxVC707MIG(implicit p: Parameters) extends LazyModule with HasXilinxVC707MIGParameters {
val device = new MemoryDevice
@@
-35,16
+28,21
@@
class XilinxVC707MIG(implicit p: Parameters) extends LazyModule with HasXilinxVC
regionType = RegionType.UNCACHED,
executable = true,
supportsWrite = TransferSizes(1, 256*8),
regionType = RegionType.UNCACHED,
executable = true,
supportsWrite = TransferSizes(1, 256*8),
- supportsRead = TransferSizes(1, 256*8),
- interleavedId = Some(0))),
+ supportsRead = TransferSizes(1, 256*8))),
beatBytes = 8)))
beatBytes = 8)))
- val xing = LazyModule(new TLAsyncCrossing)
- val toaxi4 = LazyModule(new TLToAXI4(idBits = 4))
+ val xing = LazyModule(new TLAsyncCrossing)
+ val toaxi4 = LazyModule(new TLToAXI4(beatBytes = 8))
+ val indexer = LazyModule(new AXI4IdIndexer(idBits = 4))
+ val deint = LazyModule(new AXI4Deinterleaver(p(coreplex.CacheBlockBytes)))
+ val yank = LazyModule(new AXI4UserYanker)
xing.node := node
val monitor = (toaxi4.node := xing.node)
xing.node := node
val monitor = (toaxi4.node := xing.node)
- axi4 := toaxi4.node
+ axi4 := yank.node
+ yank.node := deint.node
+ deint.node := indexer.node
+ indexer.node := toaxi4.node
lazy val module = new LazyModuleImp(this) {
val io = new Bundle {
lazy val module = new LazyModuleImp(this) {
val io = new Bundle {
@@
-58,9
+56,9
@@
class XilinxVC707MIG(implicit p: Parameters) extends LazyModule with HasXilinxVC
//pins to top level
//inouts
//pins to top level
//inouts
- io.port._inout_ddr3_dq := blackbox.io.ddr3_dq
- io.port._inout_ddr3_dqs_n := blackbox.io.ddr3_dqs_n
- io.port._inout_ddr3_dqs_p := blackbox.io.ddr3_dqs_p
+ attach(io.port.ddr3_dq,blackbox.io.ddr3_dq)
+ attach(io.port.ddr3_dqs_n,blackbox.io.ddr3_dqs_n)
+ attach(io.port.ddr3_dqs_p,blackbox.io.ddr3_dqs_p)
//outputs
io.port.ddr3_addr := blackbox.io.ddr3_addr
//outputs
io.port.ddr3_addr := blackbox.io.ddr3_addr
@@
-87,9
+85,7
@@
class XilinxVC707MIG(implicit p: Parameters) extends LazyModule with HasXilinxVC
xing.module.io.in_reset := reset
xing.module.io.out_clock := blackbox.io.ui_clk
xing.module.io.out_reset := blackbox.io.ui_clk_sync_rst
xing.module.io.in_reset := reset
xing.module.io.out_clock := blackbox.io.ui_clk
xing.module.io.out_reset := blackbox.io.ui_clk_sync_rst
- toaxi4.module.clock := blackbox.io.ui_clk
- toaxi4.module.reset := blackbox.io.ui_clk_sync_rst
- monitor.foreach { lm =>
+ (Seq(toaxi4, indexer, deint, yank) ++ monitor) foreach { lm =>
lm.module.clock := blackbox.io.ui_clk
lm.module.reset := blackbox.io.ui_clk_sync_rst
}
lm.module.clock := blackbox.io.ui_clk
lm.module.reset := blackbox.io.ui_clk_sync_rst
}