- axi_to_pcie_x1.slave := AXI4Buffer()(TLToAXI4(idBits=4)(slave))
- axi_to_pcie_x1.control := AXI4Buffer()(AXI4Fragmenter(lite=true, maxInFlight=4)(TLToAXI4(idBits=0)(control)))
- master := TLWidthWidget(8)(AXI4ToTL()(AXI4Fragmenter()(axi_to_pcie_x1.master)))
+
+ axi_to_pcie_x1.slave :=
+ AXI4Buffer()(
+ AXI4UserYanker()(
+ AXI4Deinterleaver(p(coreplex.CacheBlockBytes))(
+ AXI4IdIndexer(idBits=4)(
+ TLToAXI4(beatBytes=8)(
+ slave)))))
+
+ axi_to_pcie_x1.control :=
+ AXI4Buffer()(
+ AXI4UserYanker()(
+ AXI4Fragmenter()(
+ AXI4IdIndexer(idBits=0)(
+ TLToAXI4(beatBytes=4)(
+ control)))))
+
+ master :=
+ TLWidthWidget(8)(
+ AXI4ToTL()(
+ AXI4UserYanker(capMaxFlight=Some(8))(
+ AXI4Fragmenter()(
+ AXI4IdIndexer(idBits=0)(
+ axi_to_pcie_x1.master)))))
+