Ensure an error when reading a non-existent CSR.

[riscv-tests.git] / debug / targets / RISC-V / spike-2.cfg

diff --git a/debug/targets/RISC-V/spike-2.cfg b/debug/targets/RISC-V/spike-2.cfg
index 17526eccda20beec185e228a06ab339104d99b36..c78cf8f82d6078d7270415082156c2217fe710f6 100644 (file)
--- a/debug/targets/RISC-V/spike-2.cfg
+++ b/debug/targets/RISC-V/spike-2.cfg
@@ -15,5 +15,9 @@ target create $_TARGETNAME_1 riscv -chain-position $_CHIPNAME.cpu -coreid 1
 
 gdb_report_data_abort enable
 
+# Expose an unimplemented CSR so we can test non-existent register access
+# behavior.
+riscv expose_csrs 2288
+
 init
 reset halt