Ensure an error when reading a non-existent CSR.

diff --git a/debug/gdbserver.py b/debug/gdbserver.py
index f0385d568441b3eeb8d1d73dc5f71b19b2a7d221..c7bfbf00393fabb77a1cd1b4121e6aea8984c0f9 100755 (executable)
--- a/debug/gdbserver.py
+++ b/debug/gdbserver.py
@@ -136,6 +136,19 @@ class SimpleF18Test(SimpleRegisterTest):
     def test(self):
         self.check_reg("f18", "fs2")
 
+class SimpleNoExistTest(GdbTest):
+    def test(self):
+        try:
+            self.gdb.p("$csr2288")
+            assert False, "Reading csr2288 should have failed"
+        except testlib.CouldNotFetch:
+            pass
+        try:
+            self.gdb.p("$csr2288=5")
+            assert False, "Writing csr2288 should have failed"
+        except testlib.CouldNotFetch:
+            pass
+
 class SimpleMemoryTest(GdbTest):
     def access_test(self, size, data_type):
         assertEqual(self.gdb.p("sizeof(%s)" % data_type), size)

diff --git a/debug/targets/RISC-V/spike-1.cfg b/debug/targets/RISC-V/spike-1.cfg
index fc20b53b4341ff600c6ef375cad8660460793df9..7607b4614ec47ae63ce337ea4eb3d676ea829486 100644 (file)
--- a/debug/targets/RISC-V/spike-1.cfg
+++ b/debug/targets/RISC-V/spike-1.cfg
@@ -12,5 +12,9 @@ target create $_TARGETNAME riscv -chain-position $_TARGETNAME
 
 gdb_report_data_abort enable
 
+# Expose an unimplemented CSR so we can test non-existent register access
+# behavior.
+riscv expose_csrs 2288
+
 init
 reset halt

diff --git a/debug/targets/RISC-V/spike-2.cfg b/debug/targets/RISC-V/spike-2.cfg
index 17526eccda20beec185e228a06ab339104d99b36..c78cf8f82d6078d7270415082156c2217fe710f6 100644 (file)
--- a/debug/targets/RISC-V/spike-2.cfg
+++ b/debug/targets/RISC-V/spike-2.cfg
@@ -15,5 +15,9 @@ target create $_TARGETNAME_1 riscv -chain-position $_CHIPNAME.cpu -coreid 1
 
 gdb_report_data_abort enable
 
+# Expose an unimplemented CSR so we can test non-existent register access
+# behavior.
+riscv expose_csrs 2288
+
 init
 reset halt

diff --git a/debug/targets/RISC-V/spike-rtos.cfg b/debug/targets/RISC-V/spike-rtos.cfg
index 799e3cba3151c493e89f163e4b39bf1752897b7a..5a70f523d56afee94c668c68399e21d3f7a2a38d 100644 (file)
--- a/debug/targets/RISC-V/spike-rtos.cfg
+++ b/debug/targets/RISC-V/spike-rtos.cfg
@@ -13,5 +13,9 @@ target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos riscv
 
 gdb_report_data_abort enable
 
+# Expose an unimplemented CSR so we can test non-existent register access
+# behavior.
+riscv expose_csrs 2288
+
 init
 reset halt

diff --git a/debug/targets/SiFive/HiFive1.cfg b/debug/targets/SiFive/HiFive1.cfg
index 5bde59bb0a26f3174a666e35e5321d239d418421..8f21b4776cb5728e65a8d05cf432b98a5932afbc 100644 (file)
--- a/debug/targets/SiFive/HiFive1.cfg
+++ b/debug/targets/SiFive/HiFive1.cfg
@@ -17,6 +17,10 @@ target create $_TARGETNAME riscv -chain-position $_TARGETNAME
 $_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 8096 -work-area-backup 1
 #-rtos riscv
 
+# Expose an unimplemented CSR so we can test non-existent register access
+# behavior.
+riscv expose_csrs 2288
+
 flash bank my_first_flash fespi 0x20000000 0 0 0 $_TARGETNAME
 init
 #reset