//--------------------------------------------------------------------------------
// Auto-generated by Migen (7bc4eb1) & LiteX (35929c0f) on 2021-05-22 11:51:10
//--------------------------------------------------------------------------------
-module ls180sram4k(
+module ls180(
output wire [12:0] sdram_a,
input wire [15:0] sdram_dq_i,
output wire [15:0] sdram_dq_o,