fix up simulation to be more like VERSA_ECP5

[gram.git] / gram / simulation / simsoc.py

diff --git a/gram/simulation/simsoc.py b/gram/simulation/simsoc.py
index ba3c8396cff6068f65e8b4c9ae864d8743a43ff9..29aa35b40b18fea9403a623fa946c475b2371b34 100644 (file)
--- a/gram/simulation/simsoc.py
+++ b/gram/simulation/simsoc.py
@@ -9,7 +9,7 @@ from lambdasoc.soc.base import SoC
 
 from gram.core import gramCore
 from gram.phy.ecp5ddrphy import ECP5DDRPHY
-from gram.modules import MT41K256M16
+from gram.modules import (MT41K256M16, MT41K64M16)
 from gram.frontend.wishbone import gramWishbone
 
 from icarusecpix5platform import IcarusECPIX5Platform
@@ -26,11 +26,12 @@ class DDR3SoC(SoC, Elaboratable):
 
         ddr_pins = platform.request("ddr3", 0, dir={"dq":"-", "dqs":"-"},
             xdr={"rst": 4, "clk":4, "a":4, "ba":4, "clk_en":4, "we_n":4,
-                 "odt":4, "ras":4, "cas":4, "we":4})
+                 "cs": 4, "odt":4, "ras":4, "cas":4, "we":4})
         self.ddrphy = DomainRenamer("dramsync")(ECP5DDRPHY(ddr_pins))
         self._decoder.add(self.ddrphy.bus, addr=ddrphy_addr)
 
-        ddrmodule = MT41K256M16(clk_freq, "1:2")
+        #ddrmodule = MT41K256M16(clk_freq, "1:2")
+        ddrmodule = MT41K64M16(clk_freq, "1:2")
 
         self.dramcore = DomainRenamer("dramsync")(gramCore(
             phy=self.ddrphy,