gram.test: Use correct timing for simulations

[gram.git] / gram / test / test_common.py

diff --git a/gram/test/test_common.py b/gram/test/test_common.py
index f775ea1d1b669fcf3b2be7dde109b1fda6256df3..fdcd025cc35114d4a68ccceeddfc718479ba5544 100644 (file)
--- a/gram/test/test_common.py
+++ b/gram/test/test_common.py
@@ -22,7 +22,7 @@ class tXXDControllerTestCase(FHDLTestCase):
             dut = tXXDController(txxd)
 
             yield dut.valid.eq(1)
-            yield; yield Delay(1e-8)
+            yield; yield Delay(1e-9)
             self.assertFalse((yield dut.ready))
 
             yield dut.valid.eq(0)