split out S-mode tests and M-mode tests

[riscv-tests.git] / isa / rv64sv / illegal_cfg_nxpr.S

diff --git a/isa/rv64sv/illegal_cfg_nxpr.S b/isa/rv64sv/illegal_cfg_nxpr.S
index dc4d3a41a0435439340d5d8af0ebdf14b4befca7..51cc84ad11e8f6b7249c7cfa2af8646da1aa3473 100644 (file)
--- a/isa/rv64sv/illegal_cfg_nxpr.S
+++ b/isa/rv64sv/illegal_cfg_nxpr.S
@@ -13,9 +13,6 @@
 RVTEST_RV64SV
 RVTEST_CODE_BEGIN
 
-  la a3,handler
-  csrw stvec,a3 # set exception handler
-
   li a0,33
   vsetcfg a0
 
@@ -23,7 +20,7 @@ vtcode2:
   add x2,x2,x3
   stop
 
-handler:
+stvec_handler:
   vxcptkill
 
   li TESTNUM,2