split out S-mode tests and M-mode tests

diff --git a/env b/env
index 104ce71726ee9ae95f920b42462afb30baeeb36c..fe2bd085aaef12c043672b2bb07fc1daab9ce598 160000 (submodule)
--- a/env
+++ b/env
@@ -1 +1 @@
-Subproject commit 104ce71726ee9ae95f920b42462afb30baeeb36c
+Subproject commit fe2bd085aaef12c043672b2bb07fc1daab9ce598

diff --git a/isa/Makefile b/isa/Makefile
index 4c8481500e6b2860aff800d15c44590a2abc75b6..229a50961cee9e7e957338d0b6a072b20f3b4262 100644 (file)
--- a/isa/Makefile
+++ b/isa/Makefile
@@ -9,8 +9,10 @@ include $(isa_src_dir)/rv64uf/Makefrag
 include $(isa_src_dir)/rv64uv/Makefrag
 include $(isa_src_dir)/rv64si/Makefrag
 include $(isa_src_dir)/rv64sv/Makefrag
+include $(isa_src_dir)/rv64mi/Makefrag
 include $(isa_src_dir)/rv32ui/Makefrag
 include $(isa_src_dir)/rv32si/Makefrag
+include $(isa_src_dir)/rv32mi/Makefrag
 
 default: all
 
@@ -81,11 +83,13 @@ endef
 
 $(eval $(call compile_template,rv32ui,-m32))
 $(eval $(call compile_template,rv32si,-m32))
+$(eval $(call compile_template,rv32mi,-m32))
 $(eval $(call compile_template,rv64ui))
 $(eval $(call compile_template,rv64uf))
 $(eval $(call compile_template,rv64uv))
 $(eval $(call compile_template,rv64si))
 $(eval $(call compile_template,rv64sv))
+$(eval $(call compile_template,rv64mi))
 
 tests_dump = $(addsuffix .dump, $(tests))
 tests_hex = $(addsuffix .hex, $(tests))

diff --git a/isa/rv32mi/Makefrag b/isa/rv32mi/Makefrag
new file mode 100644 (file)
index 0000000..e6ab8c8
--- /dev/null
+++ b/isa/rv32mi/Makefrag
@@ -0,0 +1,18 @@
+#=======================================================================
+# Makefrag for rv32mi tests
+#-----------------------------------------------------------------------
+
+rv32mi_sc_tests = \
+       csr \
+       illegal \
+       ma_fetch \
+       ma_addr \
+       scall \
+       sbreak \
+       timer \
+
+rv32mi_mc_tests = \
+       ipi \
+
+rv32mi_p_tests = $(addprefix rv32mi-p-, $(rv32mi_sc_tests))
+rv32mi_pm_tests = $(addprefix rv32mi-pm-, $(rv32mi_mc_tests))

diff --git a/isa/rv32mi/csr.S b/isa/rv32mi/csr.S
new file mode 100644 (file)
index 0000000..6361f86
--- /dev/null
+++ b/isa/rv32mi/csr.S
@@ -0,0 +1,8 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64S
+#define RVTEST_RV64S RVTEST_RV32M
+#define __MACHINE_MODE
+
+#include "../rv64si/csr.S"

diff --git a/isa/rv32mi/illegal.S b/isa/rv32mi/illegal.S
new file mode 100644 (file)
index 0000000..c357ed7
--- /dev/null
+++ b/isa/rv32mi/illegal.S
@@ -0,0 +1,8 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64S
+#define RVTEST_RV64S RVTEST_RV32M
+#define __MACHINE_MODE
+
+#include "../rv64si/illegal.S"

diff --git a/isa/rv32mi/ipi.S b/isa/rv32mi/ipi.S
new file mode 100644 (file)
index 0000000..c39fc29
--- /dev/null
+++ b/isa/rv32mi/ipi.S
@@ -0,0 +1,7 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64M
+#define RVTEST_RV64M RVTEST_RV32M
+
+#include "../rv64mi/ipi.S"

diff --git a/isa/rv32mi/ma_addr.S b/isa/rv32mi/ma_addr.S
new file mode 100644 (file)
index 0000000..df5099a
--- /dev/null
+++ b/isa/rv32mi/ma_addr.S
@@ -0,0 +1,8 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64S
+#define RVTEST_RV64S RVTEST_RV32M
+#define __MACHINE_MODE
+
+#include "../rv64si/ma_addr.S"

diff --git a/isa/rv32mi/ma_fetch.S b/isa/rv32mi/ma_fetch.S
new file mode 100644 (file)
index 0000000..ec0e0f6
--- /dev/null
+++ b/isa/rv32mi/ma_fetch.S
@@ -0,0 +1,8 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64S
+#define RVTEST_RV64S RVTEST_RV32M
+#define __MACHINE_MODE
+
+#include "../rv64si/ma_fetch.S"

diff --git a/isa/rv32mi/sbreak.S b/isa/rv32mi/sbreak.S
new file mode 100644 (file)
index 0000000..c1b127d
--- /dev/null
+++ b/isa/rv32mi/sbreak.S
@@ -0,0 +1,8 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64S
+#define RVTEST_RV64S RVTEST_RV32M
+#define __MACHINE_MODE
+
+#include "../rv64si/sbreak.S"

diff --git a/isa/rv32mi/scall.S b/isa/rv32mi/scall.S
new file mode 100644 (file)
index 0000000..e5b3153
--- /dev/null
+++ b/isa/rv32mi/scall.S
@@ -0,0 +1,8 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64S
+#define RVTEST_RV64S RVTEST_RV32M
+#define __MACHINE_MODE
+
+#include "../rv64si/scall.S"

diff --git a/isa/rv32mi/timer.S b/isa/rv32mi/timer.S
new file mode 100644 (file)
index 0000000..58dac99
--- /dev/null
+++ b/isa/rv32mi/timer.S
@@ -0,0 +1,8 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64S
+#define RVTEST_RV64S RVTEST_RV32M
+#define __MACHINE_MODE
+
+#include "../rv64si/timer.S"

diff --git a/isa/rv32si/Makefrag b/isa/rv32si/Makefrag
index 70cea701876365cb22e98593d72578ebb8197fc4..e03819f9f964e963c7b0a67eb10cd7c07564d1b7 100644 (file)
--- a/isa/rv32si/Makefrag
+++ b/isa/rv32si/Makefrag
@@ -12,10 +12,4 @@ rv32si_sc_tests = \
        ma_addr \
        timer \
 
-rv32si_mc_tests = \
-       ipi \
-
 rv32si_p_tests = $(addprefix rv32si-p-, $(rv32si_sc_tests))
-rv32si_pm_tests = $(addprefix rv32si-pm-, $(rv32si_mc_tests))
-
-spike_tests += $(rv32si_p_tests) $(rv32si_pm_tests)

diff --git a/isa/rv32si/ipi.S b/isa/rv32si/ipi.S
deleted file mode 100644 (file)
index 7e11423..0000000
--- a/isa/rv32si/ipi.S
+++ /dev/null
@@ -1,7 +0,0 @@
-# See LICENSE for license details.
-
-#include "riscv_test.h"
-#undef RVTEST_RV64S
-#define RVTEST_RV64S RVTEST_RV32S
-
-#include "../rv64si/ipi.S"

diff --git a/isa/rv64mi/Makefrag b/isa/rv64mi/Makefrag
new file mode 100644 (file)
index 0000000..db40dc1
--- /dev/null
+++ b/isa/rv64mi/Makefrag
@@ -0,0 +1,21 @@
+#=======================================================================
+# Makefrag for rv64mi tests
+#-----------------------------------------------------------------------
+
+rv64mi_sc_tests = \
+       dirty \
+       csr \
+       illegal \
+       ma_fetch \
+       ma_addr \
+       scall \
+       sbreak \
+       timer \
+
+rv64mi_mc_tests = \
+       ipi \
+
+rv64mi_p_tests = $(addprefix rv64mi-p-, $(rv64mi_sc_tests))
+rv64mi_pm_tests = $(addprefix rv64mi-pm-, $(rv64mi_mc_tests))
+
+spike_tests += $(rv64mi_p_tests) $(rv64mi_pm_tests)

diff --git a/isa/rv64mi/csr.S b/isa/rv64mi/csr.S
new file mode 100644 (file)
index 0000000..77e7619
--- /dev/null
+++ b/isa/rv64mi/csr.S
@@ -0,0 +1,8 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64S
+#define RVTEST_RV64S RVTEST_RV64M
+#define __MACHINE_MODE
+
+#include "../rv64si/csr.S"

diff --git a/isa/rv64mi/dirty.S b/isa/rv64mi/dirty.S
new file mode 100644 (file)
index 0000000..f343cf9
--- /dev/null
+++ b/isa/rv64mi/dirty.S
@@ -0,0 +1,82 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# dirty.S
+#-----------------------------------------------------------------------------
+#
+# Test VM referenced and dirty bits.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64M
+RVTEST_CODE_BEGIN
+
+  # Turn on VM with superpage identity mapping
+  la a1, page_table_1
+  csrw sptbr, a1
+  sfence.vm
+  li a1, ((MSTATUS_VM & ~(MSTATUS_VM<<1)) * VM_SV43) | ((MSTATUS_PRV1 & ~(MSTATUS_PRV1<<1)) * PRV_S)
+  csrs mstatus, a1
+  la a1, 1f
+  csrw mepc, a1
+  eret
+1:
+
+  # Try a faulting store to make sure dirty bit is not set
+  li TESTNUM, 2
+  li t0, 1
+  sd t0, dummy, t1
+
+  # Load new page table
+  li TESTNUM, 3
+  la t0, page_table_2
+  csrw sptbr, t0
+  sfence.vm
+
+  # Try a non-faulting store to make sure dirty bit is set
+  sd t0, dummy, t1
+
+  # Make sure R and D bits are set
+  lw t0, page_table_2
+  li t1, PTE_R | PTE_D
+  and t0, t0, t1
+  bne t0, t1, die
+  
+  RVTEST_PASS
+
+  TEST_PASSFAIL
+
+stvec_handler:
+  csrr t0, scause
+  li t1, 2
+  bne TESTNUM, t1, 1f
+  # Make sure R bit is set
+  lw t0, page_table_1
+  li t1, PTE_R
+  and t0, t0, t1
+  bne t0, t1, die
+
+  # Make sure D bit is clear
+  lw t0, page_table_1
+  li t1, PTE_D
+  and t0, t0, t1
+  beq t0, t1, die
+
+  csrr t0, sepc
+  add t0, t0, 4
+  csrw sepc, t0
+  sret
+
+die:
+  RVTEST_FAIL
+
+.data
+.align 13
+page_table_1: .dword PTE_V | PTE_SX | PTE_SR
+dummy: .dword 0
+.align 13
+page_table_2: .dword PTE_V | PTE_SX | PTE_SR | PTE_SW
+
+RVTEST_CODE_END

diff --git a/isa/rv64mi/illegal.S b/isa/rv64mi/illegal.S
new file mode 100644 (file)
index 0000000..c5ccffd
--- /dev/null
+++ b/isa/rv64mi/illegal.S
@@ -0,0 +1,8 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64S
+#define RVTEST_RV64S RVTEST_RV64M
+#define __MACHINE_MODE
+
+#include "../rv64si/illegal.S"

diff --git a/isa/rv64mi/ipi.S b/isa/rv64mi/ipi.S
new file mode 100644 (file)
index 0000000..326476d
--- /dev/null
+++ b/isa/rv64mi/ipi.S
@@ -0,0 +1,62 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# ipi.S
+#-----------------------------------------------------------------------------
+#
+# Test interprocessor interrupts.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64M
+RVTEST_CODE_BEGIN
+
+  # enable interrupts
+  csrs mstatus, MSTATUS_IE
+
+  # get a unique core id
+  la a0, coreid
+  li a1, 1
+  amoadd.w a2, a1, (a0)
+  
+  # for now, only run this on core 0
+  1:li a3, 1
+  bgeu a2, a3, 1b
+  
+  # wait for all cores to boot
+  1: lw a1, (a0)
+  bltu a1, a3, 1b
+
+  # IPI dominoes
+  csrr a0, hartid
+  1: bnez a0, 1b
+  add a0, a0, 1
+  rem a0, a0, a3
+  csrw send_ipi, a0
+  1: j 1b
+
+mtvec_handler:
+  csrr a0, hartid
+  bnez a0, 2f
+  RVTEST_PASS
+
+  TEST_PASSFAIL
+
+  2: add a0, a0, 1
+  rem a0, a0, a3
+  csrw send_ipi, a0
+  1: j 1b
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+coreid: .word 0
+foo: .word 0
+
+RVTEST_DATA_END

diff --git a/isa/rv64mi/ma_addr.S b/isa/rv64mi/ma_addr.S
new file mode 100644 (file)
index 0000000..0448736
--- /dev/null
+++ b/isa/rv64mi/ma_addr.S
@@ -0,0 +1,8 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64S
+#define RVTEST_RV64S RVTEST_RV64M
+#define __MACHINE_MODE
+
+#include "../rv64si/ma_addr.S"

diff --git a/isa/rv64mi/ma_fetch.S b/isa/rv64mi/ma_fetch.S
new file mode 100644 (file)
index 0000000..cfcb90c
--- /dev/null
+++ b/isa/rv64mi/ma_fetch.S
@@ -0,0 +1,8 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64S
+#define RVTEST_RV64S RVTEST_RV64M
+#define __MACHINE_MODE
+
+#include "../rv64si/ma_fetch.S"

diff --git a/isa/rv64mi/sbreak.S b/isa/rv64mi/sbreak.S
new file mode 100644 (file)
index 0000000..f36a9f8
--- /dev/null
+++ b/isa/rv64mi/sbreak.S
@@ -0,0 +1,8 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64S
+#define RVTEST_RV64S RVTEST_RV64M
+#define __MACHINE_MODE
+
+#include "../rv64si/sbreak.S"

diff --git a/isa/rv64mi/scall.S b/isa/rv64mi/scall.S
new file mode 100644 (file)
index 0000000..22e9eb5
--- /dev/null
+++ b/isa/rv64mi/scall.S
@@ -0,0 +1,8 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64S
+#define RVTEST_RV64S RVTEST_RV64M
+#define __MACHINE_MODE
+
+#include "../rv64si/scall.S"

diff --git a/isa/rv64mi/timer.S b/isa/rv64mi/timer.S
new file mode 100644 (file)
index 0000000..f491530
--- /dev/null
+++ b/isa/rv64mi/timer.S
@@ -0,0 +1,8 @@
+# See LICENSE for license details.
+
+#include "riscv_test.h"
+#undef RVTEST_RV64S
+#define RVTEST_RV64S RVTEST_RV64M
+#define __MACHINE_MODE
+
+#include "../rv64si/timer.S"

diff --git a/isa/rv64si/Makefrag b/isa/rv64si/Makefrag
index 802fc5568958c7d8cbac0492aedfb8d231582e6e..f19d8404ceea07e629f412fa24d1e2c320c92cc7 100644 (file)
--- a/isa/rv64si/Makefrag
+++ b/isa/rv64si/Makefrag
@@ -10,12 +10,7 @@ rv64si_sc_tests = \
        scall \
        sbreak \
        timer \
-       dirty \
-
-rv64si_mc_tests = \
-       ipi \
 
 rv64si_p_tests = $(addprefix rv64si-p-, $(rv64si_sc_tests))
-rv64si_pm_tests = $(addprefix rv64si-pm-, $(rv64si_mc_tests))
 
-spike_tests += $(rv64si_p_tests) $(rv64si_pm_tests)
+spike_tests += $(rv64si_p_tests)

diff --git a/isa/rv64si/csr.S b/isa/rv64si/csr.S
index edaaeb3e1da32cca2f899457c8d7343a945d0e61..5d4b309510f36fe9c2740fcb07bc797f1da4b1ef 100644 (file)
--- a/isa/rv64si/csr.S
+++ b/isa/rv64si/csr.S
@@ -13,9 +13,16 @@
 RVTEST_RV64S
 RVTEST_CODE_BEGIN
 
-  # Set up stvec in case we trap.
-  la t0, stvec
-  csrw stvec, t0
+#ifdef __MACHINE_MODE
+  #define sscratch mscratch
+  #define sstatus mstatus
+  #define scause mcause
+  #define sepc mepc
+  #define stvec_handler mtvec_handler
+  #undef SSTATUS_PS
+  #define SSTATUS_PS MSTATUS_PRV1
+#endif
+
   csrwi scycle, 0
 
   csrwi sscratch, 3
@@ -31,7 +38,7 @@ RVTEST_CODE_BEGIN
   # Make sure writing the cycle counter causes an exception.
   TEST_CASE(10, a0, 255, li a0, 255; csrrw a0, cycle, x0);
 
-  # Enter user mode
+  # jump to user land
   li t0, SSTATUS_PS
   csrc sstatus, t0
   la t0, 1f
@@ -51,7 +58,7 @@ RVTEST_CODE_BEGIN
   # We should only fall through to this if scall failed.
   TEST_PASSFAIL
 
-stvec:
+stvec_handler:
   # Trapping on tests 10, 11, and 13 is usually good news.
   # Note that since the test didn't complete, TESTNUM is smaller by 1.
   li t0, 9
@@ -65,7 +72,7 @@ stvec:
   j fail
 
 privileged:
-  # Make sure CAUSE indicates a lack of privilege.
+  # Make sure scause indicates a lack of privilege.
   csrr t0, scause
   li t1, CAUSE_ILLEGAL_INSTRUCTION
   bne t0, t1, fail
@@ -76,7 +83,7 @@ privileged:
   sret
 
 syscall:
-  # Make sure CAUSE indicates a syscall.
+  # Make sure scause indicates a syscall.
   csrr t0, scause
   li t1, CAUSE_ECALL
   bne t0, t1, fail

diff --git a/isa/rv64si/dirty.S b/isa/rv64si/dirty.S
deleted file mode 100644 (file)
index e5f4db6..0000000
--- a/isa/rv64si/dirty.S
+++ /dev/null
@@ -1,84 +0,0 @@
-# See LICENSE for license details.
-
-#*****************************************************************************
-# dirty.S
-#-----------------------------------------------------------------------------
-#
-# Test VM referenced and dirty bits.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV64M
-RVTEST_CODE_BEGIN
-
-  # Turn on VM with superpage identity mapping
-  la a1, handler
-  csrw stvec, a1
-  la a1, page_table_1
-  csrw sptbr, a1
-  sfence.vm
-  li a1, ((MSTATUS_VM & ~(MSTATUS_VM<<1)) * VM_SV43) | ((MSTATUS_PRV1 & ~(MSTATUS_PRV1<<1)) * PRV_S)
-  csrs mstatus, a1
-  la a1, 1f
-  csrw mepc, a1
-  eret
-1:
-
-  # Try a faulting store to make sure dirty bit is not set
-  li TESTNUM, 2
-  li t0, 1
-  sd t0, dummy, t1
-
-  # Load new page table
-  li TESTNUM, 3
-  la t0, page_table_2
-  csrw sptbr, t0
-  sfence.vm
-
-  # Try a non-faulting store to make sure dirty bit is set
-  sd t0, dummy, t1
-
-  # Make sure R and D bits are set
-  lw t0, page_table_2
-  li t1, PTE_R | PTE_D
-  and t0, t0, t1
-  bne t0, t1, die
-  
-  RVTEST_PASS
-
-  TEST_PASSFAIL
-
-handler:
-  csrr t0, scause
-  li t1, 2
-  bne TESTNUM, t1, 1f
-  # Make sure R bit is set
-  lw t0, page_table_1
-  li t1, PTE_R
-  and t0, t0, t1
-  bne t0, t1, die
-
-  # Make sure D bit is clear
-  lw t0, page_table_1
-  li t1, PTE_D
-  and t0, t0, t1
-  beq t0, t1, die
-
-  csrr t0, sepc
-  add t0, t0, 4
-  csrw sepc, t0
-  sret
-
-die:
-  RVTEST_FAIL
-
-.data
-.align 13
-page_table_1: .dword PTE_V | PTE_SX | PTE_SR
-dummy: .dword 0
-.align 13
-page_table_2: .dword PTE_V | PTE_SX | PTE_SR | PTE_SW
-
-RVTEST_CODE_END

diff --git a/isa/rv64si/illegal.S b/isa/rv64si/illegal.S
index b068118f4af5a67fb65bd721a52f33e17d17fd57..43068b4647458cbc10e003784a158a5bd1b03a59 100644 (file)
--- a/isa/rv64si/illegal.S
+++ b/isa/rv64si/illegal.S
@@ -13,8 +13,13 @@
 RVTEST_RV64S
 RVTEST_CODE_BEGIN
 
-  la t0, stvec
-  csrw stvec, t0
+#ifdef __MACHINE_MODE
+  #define sscratch mscratch
+  #define sstatus mstatus
+  #define scause mcause
+  #define sepc mepc
+  #define stvec_handler mtvec_handler
+#endif
 
   li TESTNUM, 2
   .word 0
@@ -24,7 +29,7 @@ RVTEST_CODE_BEGIN
 
   TEST_PASSFAIL
 
-stvec:
+stvec_handler:
   li t1, CAUSE_ILLEGAL_INSTRUCTION
   csrr t0, scause
   bne t0, t1, fail

diff --git a/isa/rv64si/ipi.S b/isa/rv64si/ipi.S
deleted file mode 100644 (file)
index e45c663..0000000
--- a/isa/rv64si/ipi.S
+++ /dev/null
@@ -1,62 +0,0 @@
-# See LICENSE for license details.
-
-#*****************************************************************************
-# ipi.S
-#-----------------------------------------------------------------------------
-#
-# Test interprocessor interrupts.
-#
-
-#include "riscv_test.h"
-#include "test_macros.h"
-
-RVTEST_RV64M
-RVTEST_CODE_BEGIN
-
-  # enable interrupts
-  csrs mstatus, MSTATUS_IE
-
-  # get a unique core id
-  la a0, coreid
-  li a1, 1
-  amoadd.w a2, a1, (a0)
-  
-  # for now, only run this on core 0
-  1:li a3, 1
-  bgeu a2, a3, 1b
-  
-  # wait for all cores to boot
-  1: lw a1, (a0)
-  bltu a1, a3, 1b
-
-  # IPI dominoes
-  csrr a0, hartid
-  1: bnez a0, 1b
-  add a0, a0, 1
-  rem a0, a0, a3
-  csrw send_ipi, a0
-  1: j 1b
-
-mtvec:
-  csrr a0, hartid
-  bnez a0, 2f
-  RVTEST_PASS
-
-  TEST_PASSFAIL
-
-  2: add a0, a0, 1
-  rem a0, a0, a3
-  csrw send_ipi, a0
-  1: j 1b
-
-RVTEST_CODE_END
-
-  .data
-RVTEST_DATA_BEGIN
-
-  TEST_DATA
-
-coreid: .word 0
-foo: .word 0
-
-RVTEST_DATA_END

diff --git a/isa/rv64si/ma_addr.S b/isa/rv64si/ma_addr.S
index 19abe9618040fa060a6d3dcebcbfe54e46e24024..525e0289518d23c3435f4ebc008d5fb0fead3529 100644 (file)
--- a/isa/rv64si/ma_addr.S
+++ b/isa/rv64si/ma_addr.S
@@ -13,10 +13,18 @@
 RVTEST_RV64S
 RVTEST_CODE_BEGIN
 
-  la s0, stvec_load
+#ifdef __MACHINE_MODE
+  #define sscratch mscratch
+  #define sstatus mstatus
+  #define scause mcause
+  #define sepc mepc
+  #define stvec_handler mtvec_handler
+#endif
+
+  la s0, stvec_handler
 
-  la t0, stvec_load
-  csrw stvec, t0
+  # indicate it's a load test
+  li s1, 0
 
 #define MISALIGNED_LDST_TEST(testnum, insn, base, offset) \
   li TESTNUM, testnum; \
@@ -43,8 +51,8 @@ RVTEST_CODE_BEGIN
   MISALIGNED_LDST_TEST(16, ld, s0, 7)
 #endif
 
-  la t0, stvec_store
-  csrw stvec, t0
+  # indicate it's a store test
+  li s1, 1
 
   MISALIGNED_LDST_TEST(22,  sh,  s0, 1)
   MISALIGNED_LDST_TEST(23,  sw,  s0, 1)
@@ -64,7 +72,10 @@ RVTEST_CODE_BEGIN
   TEST_PASSFAIL
 
   .align 3
-stvec_load:
+stvec_handler:
+  bnez s1, test_store
+
+test_load:
   li t1, CAUSE_MISALIGNED_LOAD
   csrr t0, scause
   bne t0, t1, fail
@@ -73,7 +84,7 @@ stvec_load:
   csrw sepc, t0
   sret
 
-stvec_store:
+test_store:
   li t1, CAUSE_MISALIGNED_STORE
   csrr t0, scause
   bne t0, t1, fail

diff --git a/isa/rv64si/ma_fetch.S b/isa/rv64si/ma_fetch.S
index ae8377de98d0a51b7c4460e180960841e2bc118f..272a9eba7d2b596e3ad782349a570dd20cd004b8 100644 (file)
--- a/isa/rv64si/ma_fetch.S
+++ b/isa/rv64si/ma_fetch.S
@@ -13,8 +13,13 @@
 RVTEST_RV64S
 RVTEST_CODE_BEGIN
 
-  la t0, stvec
-  csrw stvec, t0
+#ifdef __MACHINE_MODE
+  #define sscratch mscratch
+  #define sstatus mstatus
+  #define scause mcause
+  #define sepc mepc
+  #define stvec_handler mtvec_handler
+#endif
 
 #ifndef __rvc
   li TESTNUM, 2
@@ -47,7 +52,7 @@ RVTEST_CODE_BEGIN
 
   TEST_PASSFAIL
 
-stvec:
+stvec_handler:
   # tests 2 and 4 should trap
   li a0, 2
   beq TESTNUM, a0, 1f

diff --git a/isa/rv64si/sbreak.S b/isa/rv64si/sbreak.S
index dbdf7ae22dcd68fcb9d82ad13c6fef201925f10d..bf38434115b57ff7d0f5d1c6b5f12c3b3d0a0dce 100644 (file)
--- a/isa/rv64si/sbreak.S
+++ b/isa/rv64si/sbreak.S
@@ -13,8 +13,13 @@
 RVTEST_RV64S
 RVTEST_CODE_BEGIN
 
-  la t0, stvec
-  csrw stvec, t0
+#ifdef __MACHINE_MODE
+  #define sscratch mscratch
+  #define sstatus mstatus
+  #define scause mcause
+  #define sepc mepc
+  #define stvec_handler mtvec_handler
+#endif
 
   li TESTNUM, 2
   sbreak
@@ -24,7 +29,7 @@ RVTEST_CODE_BEGIN
 
   TEST_PASSFAIL
 
-stvec:
+stvec_handler:
   li t1, CAUSE_BREAKPOINT
   csrr t0, scause
   bne t0, t1, fail

diff --git a/isa/rv64si/scall.S b/isa/rv64si/scall.S
index aa543e98c138471fd5ba869b098b2cced2e942b9..e1c13b6464ffcef7d3f718ea0d3b93222dc249dd 100644 (file)
--- a/isa/rv64si/scall.S
+++ b/isa/rv64si/scall.S
@@ -13,8 +13,13 @@
 RVTEST_RV64S
 RVTEST_CODE_BEGIN
 
-  la t0, stvec
-  csrw stvec, t0
+#ifdef __MACHINE_MODE
+  #define sscratch mscratch
+  #define sstatus mstatus
+  #define scause mcause
+  #define sepc mepc
+  #define stvec_handler mtvec_handler
+#endif
 
   li TESTNUM, 2
   scall
@@ -24,7 +29,7 @@ RVTEST_CODE_BEGIN
 
   TEST_PASSFAIL
 
-stvec:
+stvec_handler:
   li t1, CAUSE_ECALL
   csrr t0, scause
   bne t0, t1, fail

diff --git a/isa/rv64si/timer.S b/isa/rv64si/timer.S
index 584ced76109ed6cdd4aebc6cb57d8f9f388b1f67..c78d92227d0070dfbdc91d2f3d34c3775ccedc3f 100644 (file)
--- a/isa/rv64si/timer.S
+++ b/isa/rv64si/timer.S
@@ -1,10 +1,10 @@
 # See LICENSE for license details.
 
 #*****************************************************************************
-# ipi.S
+# timer.S
 #-----------------------------------------------------------------------------
 #
-# Test interprocessor interrupts.
+# Test timer interrupts.
 #
 
 #include "riscv_test.h"
@@ -13,16 +13,35 @@
 RVTEST_RV64S
 RVTEST_CODE_BEGIN
 
-  # clear pending IPIs then enable interrupts
+#ifdef __MACHINE_MODE
+  #define sscratch mscratch
+  #define sstatus mstatus
+  #define scause mcause
+  #define sepc mepc
+  #define stvec_handler mtvec_handler
+  #undef SSTATUS_PS
+  #define SSTATUS_PS MSTATUS_PRV1
+  #undef SSTATUS_IE
+  #define SSTATUS_IE MSTATUS_IE
+  #undef SSTATUS_TIE
+  #define SSTATUS_TIE MSTATUS_STIE
+#endif
+
   li s8, 0         # number of taken timer interrupts
   li s9, 10        # how many interrupts to run for
-  la a0, handler
-  csrw stvec, a0
   csrw stimecmp, 1
   csrw stime, 0
   li a0, SSTATUS_IE | SSTATUS_TIE
   csrs sstatus, a0
 
+  # jump to user land
+  li t0, SSTATUS_PS
+  csrc sstatus, t0
+  la t0, 1f
+  csrw sepc, t0
+  sret
+  1:
+
   # advance an LFSR 1000 times
   li s0, 1023
   li s4, 0
@@ -36,8 +55,6 @@ RVTEST_CODE_BEGIN
   add s4, s4, 1
   bltu s8, s9, 1b
 
-  csrc sstatus, SSTATUS_IE
-
   # make sure the LFSR was computed correctly
   li s1, 1023
   remu s4, s4, s1
@@ -52,7 +69,7 @@ RVTEST_CODE_BEGIN
 
   TEST_PASSFAIL
 
-handler:
+stvec_handler:
   li TESTNUM, 3
   csrr t0, scause
   bgez t0, fail
@@ -66,7 +83,13 @@ handler:
   csrw stimecmp, t0
 
   add s8, s8, 1
+  bltu s8, s9, stvec_return
+
+  li t0, SSTATUS_PS
+  csrs sstatus, t0
+  csrc sstatus, SSTATUS_IE
 
+stvec_return:
   sret
 
 .data

diff --git a/isa/rv64sv/illegal_cfg_nfpr.S b/isa/rv64sv/illegal_cfg_nfpr.S
index 03227eb2a166dd9d4b356fb6dbc0db04e25df4c6..be114cc70b138513cb4981be4c3d28538811090c 100644 (file)
--- a/isa/rv64sv/illegal_cfg_nfpr.S
+++ b/isa/rv64sv/illegal_cfg_nfpr.S
@@ -13,9 +13,6 @@
 RVTEST_RV64SV
 RVTEST_CODE_BEGIN
 
-  la a3,handler
-  csrw stvec,a3 # set exception handler
-
   li a0,33
   slli a0,a0,6
   vsetcfg a0
@@ -24,7 +21,7 @@ vtcode2:
   add x2,x2,x3
   stop
 
-handler:
+stvec_handler:
   vxcptkill
 
   li TESTNUM,2

diff --git a/isa/rv64sv/illegal_cfg_nxpr.S b/isa/rv64sv/illegal_cfg_nxpr.S
index dc4d3a41a0435439340d5d8af0ebdf14b4befca7..51cc84ad11e8f6b7249c7cfa2af8646da1aa3473 100644 (file)
--- a/isa/rv64sv/illegal_cfg_nxpr.S
+++ b/isa/rv64sv/illegal_cfg_nxpr.S
@@ -13,9 +13,6 @@
 RVTEST_RV64SV
 RVTEST_CODE_BEGIN
 
-  la a3,handler
-  csrw stvec,a3 # set exception handler
-
   li a0,33
   vsetcfg a0
 
@@ -23,7 +20,7 @@ vtcode2:
   add x2,x2,x3
   stop
 
-handler:
+stvec_handler:
   vxcptkill
 
   li TESTNUM,2

diff --git a/isa/rv64sv/illegal_inst.S b/isa/rv64sv/illegal_inst.S
index b7dfc2819adfbddfe2126c87bd3c282699d9a9b9..7e653d1f077904271e76967ba4e67d79a3f2e99d 100644 (file)
--- a/isa/rv64sv/illegal_inst.S
+++ b/isa/rv64sv/illegal_inst.S
@@ -13,9 +13,6 @@
 RVTEST_RV64SV
 RVTEST_CODE_BEGIN
 
-  la a3,handler
-  csrw stvec,a3 # set exception handler
-
   .word 0xff00002b
 
   vsetcfg 32,0
@@ -30,7 +27,7 @@ vtcode2:
   add x2,x2,x3
   stop
 
-handler:
+stvec_handler:
   vxcptkill
 
   li TESTNUM,2

diff --git a/isa/rv64sv/illegal_tvec_regid.S b/isa/rv64sv/illegal_tvec_regid.S
index a2090ac51ff17b68e3708e50a7612a04421a897d..30403baaf88c175ede1c209221e3eb4ea7885caa 100644 (file)
--- a/isa/rv64sv/illegal_tvec_regid.S
+++ b/isa/rv64sv/illegal_tvec_regid.S
@@ -21,6 +21,10 @@ RVTEST_CODE_BEGIN
 
   TEST_PASSFAIL
 
+# the handler gets rewritten for every test, but need this for the framework
+stvec_handler:
+  j fail
+
 RVTEST_CODE_END
 
   .data

diff --git a/isa/rv64sv/illegal_vt_inst.S b/isa/rv64sv/illegal_vt_inst.S
index e2164137047d0552ea6420f1a44151dd74caa625..080cd2f6b943943e27a50ee4c4a46609f33c7117 100644 (file)
--- a/isa/rv64sv/illegal_vt_inst.S
+++ b/isa/rv64sv/illegal_vt_inst.S
@@ -13,9 +13,6 @@
 RVTEST_RV64SV
 RVTEST_CODE_BEGIN
 
-  la a3,handler
-  csrw stvec,a3 # set exception handler
-
   vsetcfg 32,0
   li a3,4
   vsetvl a3,a3
@@ -38,7 +35,7 @@ vtcode2:
   add x2,x2,x3
   stop
 
-handler:
+stvec_handler:
   vxcptkill
 
   li TESTNUM,2

diff --git a/isa/rv64sv/illegal_vt_regid.S b/isa/rv64sv/illegal_vt_regid.S
index 24745dc62f99cd1f25bb0dfe0064fa432859b416..e74b614d5f345cc3ad96ca6bf89066b14cee8e63 100644 (file)
--- a/isa/rv64sv/illegal_vt_regid.S
+++ b/isa/rv64sv/illegal_vt_regid.S
@@ -23,6 +23,10 @@ RVTEST_CODE_BEGIN
 
   TEST_PASSFAIL
 
+# the handler gets rewritten for every test, but need this for the framework
+stvec_handler:
+  j fail
+
 RVTEST_CODE_END
 
   .data

diff --git a/isa/rv64sv/ma_utld.S b/isa/rv64sv/ma_utld.S
index 79b21b1d3d9b183c1c2e506645bb839d272b6963..5ea6ee6d52a92ced7b34d05fde2d4763cdc4b732 100644 (file)
--- a/isa/rv64sv/ma_utld.S
+++ b/isa/rv64sv/ma_utld.S
@@ -13,9 +13,6 @@
 RVTEST_RV64SV
 RVTEST_CODE_BEGIN
 
-  la a3,handler
-  csrw stvec,a3 # set exception handler
-
   vsetcfg 32,0
   li a3,4
   vsetvl a3,a3
@@ -34,7 +31,7 @@ vtcode2:
   add x2,x2,x3
   stop
 
-handler:
+stvec_handler:
   vxcptkill
 
   li TESTNUM,2

diff --git a/isa/rv64sv/ma_utsd.S b/isa/rv64sv/ma_utsd.S
index 9bd3cd8e6711184bcb497dbb294fb060e29be1f3..47df11bcbbce84029900b054b5fdccf104c24427 100644 (file)
--- a/isa/rv64sv/ma_utsd.S
+++ b/isa/rv64sv/ma_utsd.S
@@ -13,9 +13,6 @@
 RVTEST_RV64SV
 RVTEST_CODE_BEGIN
 
-  la a3,handler
-  csrw stvec,a3 # set exception handler
-
   vsetcfg 32,0
   li a3,4
   vsetvl a3,a3
@@ -36,7 +33,7 @@ vtcode2:
   add x2,x2,x3
   stop
 
-handler:
+stvec_handler:
   vxcptkill
 
   li TESTNUM,2

diff --git a/isa/rv64sv/ma_vld.S b/isa/rv64sv/ma_vld.S
index 85882b8b2a34a50ec17eec9ca2a9323b93d97cff..2cdc2d43dcafb1eee5b5eb98ac7f61cfc5d6156e 100644 (file)
--- a/isa/rv64sv/ma_vld.S
+++ b/isa/rv64sv/ma_vld.S
@@ -13,9 +13,6 @@
 RVTEST_RV64SV
 RVTEST_CODE_BEGIN
 
-  la a3,handler
-  csrw stvec,a3 # set exception handler
-
   vsetcfg 32,0
   li a3,4
   vsetvl a3,a3
@@ -35,7 +32,7 @@ vtcode2:
   add x2,x2,x3
   stop
 
-handler:
+stvec_handler:
   vxcptkill
 
   li TESTNUM,2

diff --git a/isa/rv64sv/ma_vsd.S b/isa/rv64sv/ma_vsd.S
index 35cb828b7182f4e4714a79b5b270d0e89805e7dc..e113f99c9f09c003d88d6b361946c6a038db4e03 100644 (file)
--- a/isa/rv64sv/ma_vsd.S
+++ b/isa/rv64sv/ma_vsd.S
@@ -13,9 +13,6 @@
 RVTEST_RV64SV
 RVTEST_CODE_BEGIN
 
-  la a3,handler
-  csrw stvec,a3 # set exception handler
-
   vsetcfg 32,0
   li a3,4
   vsetvl a3,a3
@@ -38,7 +35,7 @@ vtcode2:
   add x2,x2,x3
   stop
 
-handler:
+stvec_handler:
   vxcptkill
 
   li TESTNUM,2

diff --git a/isa/rv64sv/ma_vt_inst.S b/isa/rv64sv/ma_vt_inst.S
index d7c96b3f0c8dc0ffeb248db849a375067eeff35d..a2579425e0abf020104a7200d29cc574aca28377 100644 (file)
--- a/isa/rv64sv/ma_vt_inst.S
+++ b/isa/rv64sv/ma_vt_inst.S
@@ -13,9 +13,6 @@
 RVTEST_RV64SV
 RVTEST_CODE_BEGIN
 
-  la a3,handler
-  csrw stvec,a3 # set exception handler
-
   vsetcfg 32,0
   li a3,4
   vsetvl a3,a3
@@ -28,7 +25,7 @@ vtcode1:
   add x2,x2,x3
   stop
 
-handler:
+stvec_handler:
   vxcptkill
 
   li TESTNUM,2

diff --git a/isa/rv64sv/privileged_inst.S b/isa/rv64sv/privileged_inst.S
index 65c5288a8e7e683f08f60bdb12a1722028e0b09f..e59d361fd4562410d2288f7d05248d8a915e9984 100644 (file)
--- a/isa/rv64sv/privileged_inst.S
+++ b/isa/rv64sv/privileged_inst.S
@@ -13,9 +13,6 @@
 RVTEST_RV64SV
 RVTEST_CODE_BEGIN
 
-  la a3,handler
-  csrw stvec,a3 # set exception handler
-
   li a3, SSTATUS_PS
   csrc sstatus, a3
   la t0, 1f
@@ -30,7 +27,7 @@ vtcode2:
   add x2,x2,x3
   stop
 
-handler:
+stvec_handler:
   vxcptkill
 
   li TESTNUM,2