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split out S-mode tests and M-mode tests
[riscv-tests.git] / isa / rv64sv / illegal_inst.S
diff --git a/isa/rv64sv/illegal_inst.S b/isa/rv64sv/illegal_inst.S
index b7dfc2819adfbddfe2126c87bd3c282699d9a9b9..7e653d1f077904271e76967ba4e67d79a3f2e99d 100644 (file)
--- a/isa/rv64sv/illegal_inst.S
+++ b/isa/rv64sv/illegal_inst.S
@@ -13,9 +13,6 @@
 RVTEST_RV64SV
 RVTEST_CODE_BEGIN
 
-  la a3,handler
-  csrw stvec,a3 # set exception handler
-
   .word 0xff00002b
 
   vsetcfg 32,0
@@ -30,7 +27,7 @@ vtcode2:
   add x2,x2,x3
   stop
 
-handler:
+stvec_handler:
   vxcptkill
 
   li TESTNUM,2