split out S-mode tests and M-mode tests

[riscv-tests.git] / isa / rv64sv / illegal_vt_regid.S

diff --git a/isa/rv64sv/illegal_vt_regid.S b/isa/rv64sv/illegal_vt_regid.S
index 24745dc62f99cd1f25bb0dfe0064fa432859b416..e74b614d5f345cc3ad96ca6bf89066b14cee8e63 100644 (file)
--- a/isa/rv64sv/illegal_vt_regid.S
+++ b/isa/rv64sv/illegal_vt_regid.S
@@ -23,6 +23,10 @@ RVTEST_CODE_BEGIN
 
   TEST_PASSFAIL
 
+# the handler gets rewritten for every test, but need this for the framework
+stvec_handler:
+  j fail
+
 RVTEST_CODE_END
 
   .data