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split out S-mode tests and M-mode tests
[riscv-tests.git] / isa / rv64sv / ma_utld.S
diff --git a/isa/rv64sv/ma_utld.S b/isa/rv64sv/ma_utld.S
index 79b21b1d3d9b183c1c2e506645bb839d272b6963..5ea6ee6d52a92ced7b34d05fde2d4763cdc4b732 100644 (file)
--- a/isa/rv64sv/ma_utld.S
+++ b/isa/rv64sv/ma_utld.S
@@ -13,9 +13,6 @@
 RVTEST_RV64SV
 RVTEST_CODE_BEGIN
 
-  la a3,handler
-  csrw stvec,a3 # set exception handler
-
   vsetcfg 32,0
   li a3,4
   vsetvl a3,a3
@@ -34,7 +31,7 @@ vtcode2:
   add x2,x2,x3
   stop
 
-handler:
+stvec_handler:
   vxcptkill
 
   li TESTNUM,2