match up PLL names

[libresoc-litex.git] / libresoc / core.py

diff --git a/libresoc/core.py b/libresoc/core.py
index 478bcaf330cf239e4a4310de902da2d69e590220..f58a6fba7b4970934dc0ae62ca6094a6fb1b1ef0 100644 (file)
--- a/libresoc/core.py
+++ b/libresoc/core.py
@@ -270,12 +270,12 @@ class LibreSoC(CPU):
 
         # add clock select, pll output
         if "ls180" in variant and "pll" not in variant:
-            self.pll_18_o = Signal()
+            self.pll_vco_o = Signal()
             self.clk_sel = Signal(2)
             self.pll_ana_o = Signal()
             self.cpu_params['i_clk_sel_i'] = self.clk_sel
-            self.cpu_params['o_pll_18_o'] = self.pll_18_o
-            self.cpu_params['o_pll_testout_o'] = self.pll_ana_o
+            self.cpu_params['o_pll_vco_o'] = self.pll_vco_o
+            self.cpu_params['o_pll_test_o'] = self.pll_test_o
 
         # add wishbone buses to cpu params
         self.cpu_params.update(make_wb_bus("ibus", ibus, True))