match up PLL names

diff --git a/libresoc/core.py b/libresoc/core.py
index 478bcaf330cf239e4a4310de902da2d69e590220..f58a6fba7b4970934dc0ae62ca6094a6fb1b1ef0 100644 (file)
--- a/libresoc/core.py
+++ b/libresoc/core.py
@@ -270,12 +270,12 @@ class LibreSoC(CPU):
 
         # add clock select, pll output
         if "ls180" in variant and "pll" not in variant:
-            self.pll_18_o = Signal()
+            self.pll_vco_o = Signal()
             self.clk_sel = Signal(2)
             self.pll_ana_o = Signal()
             self.cpu_params['i_clk_sel_i'] = self.clk_sel
-            self.cpu_params['o_pll_18_o'] = self.pll_18_o
-            self.cpu_params['o_pll_testout_o'] = self.pll_ana_o
+            self.cpu_params['o_pll_vco_o'] = self.pll_vco_o
+            self.cpu_params['o_pll_test_o'] = self.pll_test_o
 
         # add wishbone buses to cpu params
         self.cpu_params.update(make_wb_bus("ibus", ibus, True))

diff --git a/ls180soc.py b/ls180soc.py
index d1d8dfef31f7a2ef36466c80c705d25cc45781ed..6321b01dc19f27cbd0139811f6d94150f9562e25 100755 (executable)
--- a/ls180soc.py
+++ b/ls180soc.py
@@ -427,12 +427,12 @@ class LibreSoCSim(SoCCore):
         if hasattr(self.cpu, "clk_sel"):
             # PLL/Clock Select
             clksel_i = platform.request("sys_clksel_i")
-            pll18_o = platform.request("sys_pll_testout_o")
-            pll_ana_o = platform.request("sys_pll_vco_o")
+            pll_test_o = platform.request("sys_pll_testout_o")
+            pll_vco_o = platform.request("sys_pll_vco_o")
 
             self.comb += self.cpu.clk_sel.eq(clksel_i) # allow clock src select
-            self.comb += pll18_o.eq(self.cpu.pll_18_o) # "test feed" from PLL
-            self.comb += pll_ana_o.eq(self.cpu.pll_ana_o) # PLL lock flag
+            self.comb += pll_test_o.eq(self.cpu.pll_test_o) # "test" from PLL
+            self.comb += pll_vco_o.eq(self.cpu.pll_vco_o) # PLL lock flag
 
         #ram_init = []