Update all boards to use default_clk.

[nmigen-boards.git] / nmigen_boards / versa_ecp5.py

diff --git a/nmigen_boards/versa_ecp5.py b/nmigen_boards/versa_ecp5.py
index 35b28be00e8312dc15dcb89cfe5d10fea2ad811b..4b2b9f0a1b0d757b843725d831d11e4d8d63f1d7 100644 (file)
--- a/nmigen_boards/versa_ecp5.py
+++ b/nmigen_boards/versa_ecp5.py
@@ -10,10 +10,11 @@ __all__ = ["VersaECP5Platform"]
 
 
 class VersaECP5Platform(LatticeECP5Platform):
-    device     = "LFE5UM-45F"
-    package    = "BG381"
-    speed      = "8"
-    resources  = [
+    device      = "LFE5UM-45F"
+    package     = "BG381"
+    speed       = "8"
+    default_clk = "clk100"
+    resources   = [
         Resource("rst", 0, PinsN("T1", dir="i"), Attrs(IO_TYPE="LVCMOS33")),
         Resource("clk100", 0, DiffPairs("P3", "P4", dir="i"),
                  Clock(100e6), Attrs(IO_TYPE="LVDS")),
@@ -179,4 +180,4 @@ class VersaECP5Platform(LatticeECP5Platform):
 
 if __name__ == "__main__":
     from ._blinky import build_and_program
-    build_and_program(VersaECP5Platform, "clk100")
+    build_and_program(VersaECP5Platform)