Add debug_module bus device.

[riscv-isa-sim.git] / riscv / execute.cc

diff --git a/riscv/execute.cc b/riscv/execute.cc
index 1796c3884ba2a2d2761ddd7512dada25c7cd4b92..25d1d51f2aa5507b96048d1491e1c4ca70f98961 100644 (file)
--- a/riscv/execute.cc
+++ b/riscv/execute.cc
@@ -2,6 +2,7 @@
 
 #include "processor.h"
 #include "mmu.h"
+#include "sim.h"
 #include <cassert>
 
 
@@ -53,10 +54,18 @@ static reg_t execute_insn(processor_t* p, reg_t pc, insn_fetch_t fetch)
 // fetch/decode/execute loop
 void processor_t::step(size_t n)
 {
-  if (state.dcsr.debugint && state.dcsr.cause == DCSR_CAUSE_NONE) {
+  // TODO: get_interrupt() isn't super fast. Does that matter?
+  if (state.dcsr.cause == DCSR_CAUSE_NONE &&
+      sim->debug_module.get_interrupt(id)) {
     enter_debug_mode(DCSR_CAUSE_DEBUGINT);
   }
 
+  if (state.dcsr.cause != DCSR_CAUSE_NONE) {
+    // In Debug Mode, just do 100 steps at a time. Otherwise we're going to be
+    // spinning the rest of the time anyway.
+    n = std::max(n, (size_t) 100);
+  }
+
   while (n > 0) {
     size_t instret = 0;
     reg_t pc = state.pc;