make NaN behavior consistent with hardfloat

[riscv-isa-sim.git] / riscv / insns / fadd_d.h

diff --git a/riscv/insns/fadd_d.h b/riscv/insns/fadd_d.h
index 48c76a77ac5b3e5bec563ff63ae7d81eae2e44a0..dcc6413528851a1a21a777df63895d297055af74 100644 (file)
--- a/riscv/insns/fadd_d.h
+++ b/riscv/insns/fadd_d.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = f64_add(FRS1, FRS2);
+FRD = f64_mulAdd(FRS1, 0x3ff0000000000000ULL, FRS2);
 set_fp_exceptions;