make NaN behavior consistent with hardfloat

diff --git a/riscv/insns/fadd_d.h b/riscv/insns/fadd_d.h
index 48c76a77ac5b3e5bec563ff63ae7d81eae2e44a0..dcc6413528851a1a21a777df63895d297055af74 100644 (file)
--- a/riscv/insns/fadd_d.h
+++ b/riscv/insns/fadd_d.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = f64_add(FRS1, FRS2);
+FRD = f64_mulAdd(FRS1, 0x3ff0000000000000ULL, FRS2);
 set_fp_exceptions;

diff --git a/riscv/insns/fadd_s.h b/riscv/insns/fadd_s.h
index 2fd5429c481d54f95087ba41460354ad66015c27..952d1a73d55dcb29b861c399a5d598bd40151005 100644 (file)
--- a/riscv/insns/fadd_s.h
+++ b/riscv/insns/fadd_s.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = f32_add(FRS1, FRS2);
+FRD = f32_mulAdd(FRS1, 0x3f800000, FRS2);
 set_fp_exceptions;

diff --git a/riscv/insns/fmul_d.h b/riscv/insns/fmul_d.h
index a8adedd1bc17563aee013aef3f4bc76a0827b14f..a1462d3e1631b0f74a8f914c7f75ca3fd2acabe6 100644 (file)
--- a/riscv/insns/fmul_d.h
+++ b/riscv/insns/fmul_d.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = f64_mul(FRS1, FRS2);
+FRD = f64_mulAdd(FRS1, FRS2, (FRS1 ^ FRS2) & (uint64_t)INT64_MIN);
 set_fp_exceptions;

diff --git a/riscv/insns/fmul_s.h b/riscv/insns/fmul_s.h
index 64755785991ec37d191962fc65975c854397a8ee..a954c3d1438f691fcae83246089906f2f3519681 100644 (file)
--- a/riscv/insns/fmul_s.h
+++ b/riscv/insns/fmul_s.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = f32_mul(FRS1, FRS2);
+FRD = f32_mulAdd(FRS1, FRS2, (FRS1 ^ FRS2) & (uint32_t)INT32_MIN);
 set_fp_exceptions;

diff --git a/riscv/insns/fnmadd_d.h b/riscv/insns/fnmadd_d.h
index 1e2ee27a89db1a1a8bea846415e4fa07b341bfc9..9529aebe46b0cdc35e4e615ba8accbb61b8828cc 100644 (file)
--- a/riscv/insns/fnmadd_d.h
+++ b/riscv/insns/fnmadd_d.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = f64_mulAdd(FRS1, FRS2, FRS3) ^ (uint64_t)INT64_MIN;
+FRD = f64_mulAdd(FRS1 ^ (uint64_t)INT64_MIN, FRS2, FRS3 ^ (uint64_t)INT64_MIN);
 set_fp_exceptions;

diff --git a/riscv/insns/fnmadd_s.h b/riscv/insns/fnmadd_s.h
index 78abb78f11fc73a28eabf8d0d2da06e17f3dfa19..2052b938ddd568786445ea793e6bb45fd600a768 100644 (file)
--- a/riscv/insns/fnmadd_s.h
+++ b/riscv/insns/fnmadd_s.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = f32_mulAdd(FRS1, FRS2, FRS3) ^ (uint32_t)INT32_MIN;
+FRD = f32_mulAdd(FRS1 ^ (uint32_t)INT32_MIN, FRS2, FRS3 ^ (uint32_t)INT32_MIN);
 set_fp_exceptions;

diff --git a/riscv/insns/fnmsub_d.h b/riscv/insns/fnmsub_d.h
index ae643a56be09b037b110d4e62096689a54b0edbb..31a5b394036c9a6b488eda0149fe99ba493a85f1 100644 (file)
--- a/riscv/insns/fnmsub_d.h
+++ b/riscv/insns/fnmsub_d.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = f64_mulAdd(FRS1, FRS2, FRS3 ^ (uint64_t)INT64_MIN) ^ (uint64_t)INT64_MIN;
+FRD = f64_mulAdd(FRS1 ^ (uint64_t)INT64_MIN, FRS2, FRS3);
 set_fp_exceptions;

diff --git a/riscv/insns/fnmsub_s.h b/riscv/insns/fnmsub_s.h
index cbb70ba35d7ad64f30afeed8c4d70a10ff308a89..811a35a6ef2c4f5ca1c3fec69ce3487f43154d71 100644 (file)
--- a/riscv/insns/fnmsub_s.h
+++ b/riscv/insns/fnmsub_s.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = f32_mulAdd(FRS1, FRS2, FRS3 ^ (uint32_t)INT32_MIN) ^ (uint32_t)INT32_MIN;
+FRD = f32_mulAdd(FRS1 ^ (uint32_t)INT32_MIN, FRS2, FRS3);
 set_fp_exceptions;

diff --git a/riscv/insns/fsub_d.h b/riscv/insns/fsub_d.h
index e25eebbdc281b86f4d5aad2974dfcee16be4789a..fcabe0e537849df5702edb1952b5c4a7c92f5134 100644 (file)
--- a/riscv/insns/fsub_d.h
+++ b/riscv/insns/fsub_d.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = f64_sub(FRS1, FRS2);
+FRD = f64_mulAdd(FRS1, 0x3ff0000000000000ULL, FRS2 ^ (uint64_t)INT64_MIN);
 set_fp_exceptions;

diff --git a/riscv/insns/fsub_s.h b/riscv/insns/fsub_s.h
index 6c64d0435dff9f28e99c7d2d8dfec0c34a0e7674..1ff72d2e1714eb91dee0f11dfd75bd22751effd0 100644 (file)
--- a/riscv/insns/fsub_s.h
+++ b/riscv/insns/fsub_s.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = f32_sub(FRS1, FRS2);
+FRD = f32_mulAdd(FRS1, 0x3f800000, FRS2 ^ (uint32_t)INT32_MIN);
 set_fp_exceptions;

diff --git a/softfloat/f64_to_i64.c b/softfloat/f64_to_i64.c
index 89663eebf4f3babb545907c437f5e3ca29ea9ca2..676e944dd6ceb48ada3d224be07ea9281db25976 100755 (executable)
--- a/softfloat/f64_to_i64.c
+++ b/softfloat/f64_to_i64.c
@@ -29,7 +29,7 @@ int_fast64_t f64_to_i64( float64_t a, int_fast8_t roundingMode, bool exact )
             return\r
                 ! sign\r
                     || ( ( exp == 0x7FF )\r
-                             && ( sig != UINT64_C( 0x0010000000000000 ) ) )\r
+                             && fracF64UI( uiA ) )\r
                     ? INT64_C( 0x7FFFFFFFFFFFFFFF )\r
                     : - INT64_C( 0x7FFFFFFFFFFFFFFF ) - 1;\r
         }\r