make NaN behavior consistent with hardfloat

[riscv-isa-sim.git] / riscv / insns / fnmadd_d.h

diff --git a/riscv/insns/fnmadd_d.h b/riscv/insns/fnmadd_d.h
index 1e2ee27a89db1a1a8bea846415e4fa07b341bfc9..9529aebe46b0cdc35e4e615ba8accbb61b8828cc 100644 (file)
--- a/riscv/insns/fnmadd_d.h
+++ b/riscv/insns/fnmadd_d.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = f64_mulAdd(FRS1, FRS2, FRS3) ^ (uint64_t)INT64_MIN;
+FRD = f64_mulAdd(FRS1 ^ (uint64_t)INT64_MIN, FRS2, FRS3 ^ (uint64_t)INT64_MIN);
 set_fp_exceptions;