make NaN behavior consistent with hardfloat

[riscv-isa-sim.git] / riscv / insns / fnmsub_d.h

diff --git a/riscv/insns/fnmsub_d.h b/riscv/insns/fnmsub_d.h
index ae643a56be09b037b110d4e62096689a54b0edbb..31a5b394036c9a6b488eda0149fe99ba493a85f1 100644 (file)
--- a/riscv/insns/fnmsub_d.h
+++ b/riscv/insns/fnmsub_d.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = f64_mulAdd(FRS1, FRS2, FRS3 ^ (uint64_t)INT64_MIN) ^ (uint64_t)INT64_MIN;
+FRD = f64_mulAdd(FRS1 ^ (uint64_t)INT64_MIN, FRS2, FRS3);
 set_fp_exceptions;