make NaN behavior consistent with hardfloat

[riscv-isa-sim.git] / riscv / insns / fnmsub_s.h

diff --git a/riscv/insns/fnmsub_s.h b/riscv/insns/fnmsub_s.h
index cbb70ba35d7ad64f30afeed8c4d70a10ff308a89..811a35a6ef2c4f5ca1c3fec69ce3487f43154d71 100644 (file)
--- a/riscv/insns/fnmsub_s.h
+++ b/riscv/insns/fnmsub_s.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = f32_mulAdd(FRS1, FRS2, FRS3 ^ (uint32_t)INT32_MIN) ^ (uint32_t)INT32_MIN;
+FRD = f32_mulAdd(FRS1 ^ (uint32_t)INT32_MIN, FRS2, FRS3);
 set_fp_exceptions;