make NaN behavior consistent with hardfloat

[riscv-isa-sim.git] / riscv / insns / fsub_s.h

diff --git a/riscv/insns/fsub_s.h b/riscv/insns/fsub_s.h
index 6c64d0435dff9f28e99c7d2d8dfec0c34a0e7674..1ff72d2e1714eb91dee0f11dfd75bd22751effd0 100644 (file)
--- a/riscv/insns/fsub_s.h
+++ b/riscv/insns/fsub_s.h
@@ -1,4 +1,4 @@
 require_fp;
 softfloat_roundingMode = RM;
-FRD = f32_sub(FRS1, FRS2);
+FRD = f32_mulAdd(FRS1, 0x3f800000, FRS2 ^ (uint32_t)INT32_MIN);
 set_fp_exceptions;