Add debug_module bus device.

[riscv-isa-sim.git] / riscv / processor.cc

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 7c5c0fbfac8c583ff47fa00b0576560295d918bb..3cb2f5a993f828e077923d65f7066c6c15444fbd 100644 (file)
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -8,6 +8,7 @@
 #include "mmu.h"
 #include "htif.h"
 #include "disasm.h"
+#include "gdbserver.h"
 #include <cinttypes>
 #include <cmath>
 #include <cstdlib>
@@ -119,11 +120,6 @@ void state_t::reset()
   load_reservation = -1;
 }
 
-void processor_t::set_debug_int()
-{
-  state.dcsr.debugint = true;
-}
-
 void processor_t::set_debug(bool value)
 {
   debug = value;
@@ -481,7 +477,7 @@ reg_t processor_t::get_csr(int which)
           (0 << DCSR_FULLRESET_OFFSET) |
           (state.dcsr.prv << DCSR_PRV_OFFSET) |
           (state.dcsr.step << DCSR_STEP_OFFSET) |
-          (state.dcsr.debugint << DCSR_DEBUGINT_OFFSET) |
+          (sim->debug_module.get_interrupt(id) << DCSR_DEBUGINT_OFFSET) |
           (0 << DCSR_STOPCYCLE_OFFSET) |
           (0 << DCSR_STOPTIME_OFFSET) |
           (state.dcsr.ebreakm << DCSR_EBREAKM_OFFSET) |