Make -H halt the core right out of reset.

[riscv-isa-sim.git] / riscv / sim.cc

diff --git a/riscv/sim.cc b/riscv/sim.cc
index 4b4eed4ddc2369c2cfcf9aee6df6b10e2d4b41d3..d17289d5afc676b4ed8c7a6a5406b05f0407495a 100644 (file)
--- a/riscv/sim.cc
+++ b/riscv/sim.cc
@@ -47,9 +47,7 @@ sim_t::sim_t(const char* isa, size_t nprocs, size_t mem_mb, bool halted,
   debug_mmu = new mmu_t(this, NULL);
 
   for (size_t i = 0; i < procs.size(); i++) {
-    procs[i] = new processor_t(isa, this, i);
-    if (halted)
-      procs[i]->enter_debug_mode(DCSR_CAUSE_HALT);
+    procs[i] = new processor_t(isa, this, i, halted);
   }
 
   rtc.reset(new rtc_t(procs));