revamp hwacha; now runs in physical mode

[riscv-isa-sim.git] / riscv / spike.cc

diff --git a/riscv/spike.cc b/riscv/spike.cc
index 0ab1616a9e131fb2e84825bac6f4ef052ed31d01..fb2b7da164fc50630cab9f14d34e45521239769c 100644 (file)
--- a/riscv/spike.cc
+++ b/riscv/spike.cc
@@ -23,6 +23,7 @@ static void help()
   fprintf(stderr, "  --ic=<S>:<W>:<B>   Instantiate a cache model with S sets,\n");
   fprintf(stderr, "  --dc=<S>:<W>:<B>     W ways, and B-byte blocks (with S and\n");
   fprintf(stderr, "  --l2=<S>:<W>:<B>     B both powers of 2).\n");
+  fprintf(stderr, "  --extension=<name> Specify RoCC Extension\n");
   exit(1);
 }