use SimpleHandshake instead of UnbufferedPipeline

[ieee754fpu.git] / src / add / fpadd / pipeline.py

diff --git a/src/add/fpadd/pipeline.py b/src/add/fpadd/pipeline.py
index 45b943eaa12641a496e8787b4ee16d7df5b43b8c..6917b67865b3789890220deff81e1d71d3ebe1da 100644 (file)
--- a/src/add/fpadd/pipeline.py
+++ b/src/add/fpadd/pipeline.py
@@ -5,7 +5,7 @@
 from nmigen import Module
 from nmigen.cli import main, verilog
 
-from singlepipe import (ControlBase, UnbufferedPipeline, PassThroughStage)
+from singlepipe import (ControlBase, SimpleHandshake, PassThroughStage)
 from multipipe import CombMuxOutPipe
 from multipipe import PriorityCombMuxInPipe