use SimpleHandshake instead of UnbufferedPipeline

diff --git a/src/add/fpadd/addstages.py b/src/add/fpadd/addstages.py
index 626a0c0d3cc97be1cef2ba7eb8685bc63c928c96..f5703aeceaacd6c99855b9977aab4d95a8432b62 100644 (file)
--- a/src/add/fpadd/addstages.py
+++ b/src/add/fpadd/addstages.py
@@ -5,7 +5,7 @@
 from nmigen import Module
 from nmigen.cli import main, verilog
 
-from singlepipe import (StageChain, UnbufferedPipeline,
+from singlepipe import (StageChain, SimpleHandshake,
                         PassThroughStage)
 
 from fpbase import FPState
@@ -16,13 +16,13 @@ from fpadd.add0 import FPAddStage0Mod
 from fpadd.add1 import FPAddStage1Mod
 
 
-class FPAddAlignSingleAdd(FPState, UnbufferedPipeline):
+class FPAddAlignSingleAdd(FPState, SimpleHandshake):
 
     def __init__(self, width, id_wid):
         FPState.__init__(self, "align")
         self.width = width
         self.id_wid = id_wid
-        UnbufferedPipeline.__init__(self, self) # pipeline is its own stage
+        SimpleHandshake.__init__(self, self) # pipeline is its own stage
         self.a1o = self.ospec()
 
     def ispec(self):

diff --git a/src/add/fpadd/pipeline.py b/src/add/fpadd/pipeline.py
index 45b943eaa12641a496e8787b4ee16d7df5b43b8c..6917b67865b3789890220deff81e1d71d3ebe1da 100644 (file)
--- a/src/add/fpadd/pipeline.py
+++ b/src/add/fpadd/pipeline.py
@@ -5,7 +5,7 @@
 from nmigen import Module
 from nmigen.cli import main, verilog
 
-from singlepipe import (ControlBase, UnbufferedPipeline, PassThroughStage)
+from singlepipe import (ControlBase, SimpleHandshake, PassThroughStage)
 from multipipe import CombMuxOutPipe
 from multipipe import PriorityCombMuxInPipe
 

diff --git a/src/add/fpadd/specialcases.py b/src/add/fpadd/specialcases.py
index 5c5c7bcd830cfff3831137e14cd6fff506be9a83..6f9d1a08575773c3e57139c480a1b8b84ed5b677 100644 (file)
--- a/src/add/fpadd/specialcases.py
+++ b/src/add/fpadd/specialcases.py
@@ -7,7 +7,7 @@ from nmigen.cli import main, verilog
 from math import log
 
 from fpbase import FPNumDecode
-from singlepipe import UnbufferedPipeline, StageChain
+from singlepipe import SimpleHandshake, StageChain
 
 from fpbase import FPState, FPID
 from fpcommon.getop import FPADDBaseData
@@ -176,7 +176,7 @@ class FPAddSpecialCases(FPState):
             m.next = "denormalise"
 
 
-class FPAddSpecialCasesDeNorm(FPState, UnbufferedPipeline):
+class FPAddSpecialCasesDeNorm(FPState, SimpleHandshake):
     """ special cases: NaNs, infs, zeros, denormalised
         NOTE: some of these are unique to add.  see "Special Operations"
         https://steve.hollasch.net/cgindex/coding/ieeefloat.html
@@ -186,7 +186,7 @@ class FPAddSpecialCasesDeNorm(FPState, UnbufferedPipeline):
         FPState.__init__(self, "special_cases")
         self.width = width
         self.id_wid = id_wid
-        UnbufferedPipeline.__init__(self, self) # pipe is its own stage
+        SimpleHandshake.__init__(self, self) # pipe is its own stage
         self.out = self.ospec()
 
     def ispec(self):

diff --git a/src/add/fpadd/statemachine.py b/src/add/fpadd/statemachine.py
index 9e13205fe49b21ffc079585d506f3455d2ce3a15..1e45cedde540015463c1727e3b507046a8aa179a 100644 (file)
--- a/src/add/fpadd/statemachine.py
+++ b/src/add/fpadd/statemachine.py
@@ -8,7 +8,7 @@ from math import log
 
 from fpbase import FPOp
 from fpbase import Trigger
-from singlepipe import (StageChain, UnbufferedPipeline)
+from singlepipe import (StageChain, SimpleHandshake)
 
 from fpbase import FPState, FPID
 from fpcommon.getop import (FPGetOp, FPADDBaseData, FPGet2Op)

diff --git a/src/add/fpcommon/getop.py b/src/add/fpcommon/getop.py
index 607384318b1e136ae7fb586f78c5655232c0cc5b..8cf5e42166c1046a1a868ec0efc54d27e23c8437 100644 (file)
--- a/src/add/fpcommon/getop.py
+++ b/src/add/fpcommon/getop.py
@@ -9,7 +9,7 @@ from math import log
 
 from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase, FPNumBase
 from fpbase import MultiShiftRMerge, Trigger
-from singlepipe import (ControlBase, StageChain, UnbufferedPipeline,
+from singlepipe import (ControlBase, StageChain, SimpleHandshake,
                         PassThroughStage)
 from multipipe import CombMuxOutPipe
 from multipipe import PriorityCombMuxInPipe

diff --git a/src/add/fpcommon/normtopack.py b/src/add/fpcommon/normtopack.py
index 235d880700046bc353d17ee6f572d0f85dcff61e..14814669c857a4d9d9579c725ccac9d742d68d29 100644 (file)
--- a/src/add/fpcommon/normtopack.py
+++ b/src/add/fpcommon/normtopack.py
@@ -4,7 +4,7 @@
 
 #from nmigen.cli import main, verilog
 
-from singlepipe import StageChain, UnbufferedPipeline
+from singlepipe import StageChain, SimpleHandshake
 
 from fpbase import FPState, FPID
 from fpcommon.postcalc import FPAddStage1Data
@@ -14,13 +14,13 @@ from fpcommon.corrections import FPCorrectionsMod
 from fpcommon.pack import FPPackData, FPPackMod
 
 
-class FPNormToPack(FPState, UnbufferedPipeline):
+class FPNormToPack(FPState, SimpleHandshake):
 
     def __init__(self, width, id_wid):
         FPState.__init__(self, "normalise_1")
         self.id_wid = id_wid
         self.width = width
-        UnbufferedPipeline.__init__(self, self) # pipeline is its own stage
+        SimpleHandshake.__init__(self, self) # pipeline is its own stage
 
     def ispec(self):
         return FPAddStage1Data(self.width, self.id_wid) # Norm1ModSingle ispec

diff --git a/src/add/test_inout_mux_pipe.py b/src/add/test_inout_mux_pipe.py
index d0ff6489212935c2a3c2bab2fcb93cc19ff894cc..92b6f53f3b724ca73567b63c8ec9952cae97494c 100644 (file)
--- a/src/add/test_inout_mux_pipe.py
+++ b/src/add/test_inout_mux_pipe.py
@@ -13,7 +13,7 @@ from nmigen.cli import verilog, rtlil
 
 from multipipe import CombMultiOutPipeline, CombMuxOutPipe
 from multipipe import PriorityCombMuxInPipe
-from singlepipe import UnbufferedPipeline
+from singlepipe import SimpleHandshake
 
 
 class PassData: # (Value):
@@ -50,9 +50,9 @@ class PassThroughStage:
 
 
 
-class PassThroughPipe(UnbufferedPipeline):
+class PassThroughPipe(SimpleHandshake):
     def __init__(self):
-        UnbufferedPipeline.__init__(self, PassThroughStage())
+        SimpleHandshake.__init__(self, PassThroughStage())
 
 
 class InputTest:

diff --git a/src/add/test_outmux_pipe.py b/src/add/test_outmux_pipe.py
index 67b0313240d428ad1e4863b850a030561138dc1d..7c25f38498c6b23c58342bdcde251268d855c475 100644 (file)
--- a/src/add/test_outmux_pipe.py
+++ b/src/add/test_outmux_pipe.py
@@ -5,7 +5,7 @@ from nmigen.compat.sim import run_simulation
 from nmigen.cli import verilog, rtlil
 
 from multipipe import CombMuxOutPipe
-from singlepipe import UnbufferedPipeline
+from singlepipe import SimpleHandshake
 
 
 class PassInData:
@@ -43,9 +43,9 @@ class PassThroughDataStage:
 
 
 
-class PassThroughPipe(UnbufferedPipeline):
+class PassThroughPipe(SimpleHandshake):
     def __init__(self):
-        UnbufferedPipeline.__init__(self, PassThroughDataStage())
+        SimpleHandshake.__init__(self, PassThroughDataStage())