Turned the normalise_2 verilog state into nmigen

[ieee754fpu.git] / src / add / nmigen_add_experiment.py

diff --git a/src/add/nmigen_add_experiment.py b/src/add/nmigen_add_experiment.py
index c197d735ed531d73a1671a9d2ecedd8cc1daa4cb..df100d1cf62f7317ed97d4491ad7f90a3a0d5e40 100644 (file)
--- a/src/add/nmigen_add_experiment.py
+++ b/src/add/nmigen_add_experiment.py
@@ -251,6 +251,20 @@ class FPADD:
                         round_bit.eq(tot[1]),
                         sticky.eq(tot[0])
                 ]
+
+            with m.State("normalise_2"):
+                with m.If(z_e < -126):
+                    m.d.sync +=[
+                        z_e.eq(z_e + 1),
+                        z_m.eq(z_m >> 1),
+                        guard.eq(z_m[0]),
+                        round_bit.eq(guard),
+                        sticky.eq(sticky | round_bit)
+                ]
+
+                with m.Else():
+                    m.next = "round"
+
         return m
 
 """