scoreboard 6600 experimentation

[soc.git] / src / experiment / compalu.py

diff --git a/src/experiment/compalu.py b/src/experiment/compalu.py
index a240a6b458f9330b13d41f48d35ed0febb3f027f..b4df27e5181a9193599ef4bd3cc834bba5eee5cb 100644 (file)
--- a/src/experiment/compalu.py
+++ b/src/experiment/compalu.py
@@ -10,6 +10,7 @@ class ComputationUnitNoDelay(Elaboratable):
         self.rwid = rwid
         self.alu = alu
 
+        self.counter = Signal(3)
         self.go_rd_i = Signal(reset_less=True) # go read in
         self.go_wr_i = Signal(reset_less=True) # go write in
         self.issue_i = Signal(reset_less=True) # fn issue in
@@ -33,9 +34,9 @@ class ComputationUnitNoDelay(Elaboratable):
         # is in effect a "3-way revolving door".  At no time may all 3
         # latches be set at the same time.
 
-        # opcode latch (not using go_rd_i)
-        m.d.comb += opc_l.s.eq(self.go_wr_i)
-        m.d.comb += opc_l.r.eq(self.issue_i)
+        # opcode latch (not using go_rd_i) - inverted so that busy resets to 0
+        m.d.comb += opc_l.s.eq(self.issue_i) # XXX NOTE: INVERTED FROM book!
+        m.d.comb += opc_l.r.eq(self.go_wr_i) # XXX NOTE: INVERTED FROM book!
 
         # src operand latch (not using go_wr_i)
         m.d.comb += src_l.s.eq(self.issue_i)
@@ -50,8 +51,14 @@ class ComputationUnitNoDelay(Elaboratable):
         # XXX
 
         # outputs
-        m.d.comb += self.busy_o.eq(opc_l.qn) # busy out
-        m.d.comb += self.req_rel_o.eq(req_l.q & opc_l.qn) # request release out
+        m.d.comb += self.busy_o.eq(opc_l.q) # busy out
+
+        with m.If(req_l.qn & opc_l.q & (self.counter == 0)):
+            m.d.sync += self.counter.eq(5)
+        with m.If(self.counter > 0):
+            m.d.sync += self.counter.eq(self.counter - 1)
+        with m.If((self.counter == 1) | (self.counter == 0)):
+            m.d.comb += self.req_rel_o.eq(req_l.q & opc_l.q) # req release out
 
         # create a latch/register for src1/src2
         latchregister(m, self.src1_i, self.alu.a, src_l.q)
@@ -60,7 +67,7 @@ class ComputationUnitNoDelay(Elaboratable):
         #    m.d.comb += self.alu.op.eq(self.oper_i)
 
         # create a latch/register for the operand
-        latchregister(m, self.oper_i, self.alu.op, opc_l.q)
+        latchregister(m, self.oper_i, self.alu.op, src_l.q)
 
         # and one for the output from the ALU
         data_o = Signal(self.rwid, reset_less=True) # Dest register