from nmigen.cli import verilog, rtlil
from nmigen import Module, Signal, Elaboratable
-from nmutil.latch import SRLatch
+from nmutil.latch import SRLatch, latchregister
class ComputationUnitNoDelay(Elaboratable):
self.rwid = rwid
self.alu = alu
+ self.counter = Signal(3)
self.go_rd_i = Signal(reset_less=True) # go read in
self.go_wr_i = Signal(reset_less=True) # go write in
self.issue_i = Signal(reset_less=True) # fn issue in
# is in effect a "3-way revolving door". At no time may all 3
# latches be set at the same time.
- # opcode latch (not using go_rd_i)
- m.d.comb += opc_l.s.eq(self.go_wr_i)
- m.d.comb += opc_l.r.eq(self.issue_i)
+ # opcode latch (not using go_rd_i) - inverted so that busy resets to 0
+ m.d.comb += opc_l.s.eq(self.issue_i) # XXX NOTE: INVERTED FROM book!
+ m.d.comb += opc_l.r.eq(self.go_wr_i) # XXX NOTE: INVERTED FROM book!
# src operand latch (not using go_wr_i)
m.d.comb += src_l.s.eq(self.issue_i)
# XXX
# outputs
- m.d.comb += self.busy_o.eq(opc_l.qn) # busy out
- m.d.comb += self.req_rel_o.eq(req_l.q & opc_l.qn) # request release out
-
- with m.If(src_l.q):
- m.d.comb += self.alu.a.eq(self.src1_i)
- m.d.comb += self.alu.b.eq(self.src2_i)
- with m.Else():
- m.d.comb += self.alu.a.eq(self.alu.a)
- m.d.comb += self.alu.b.eq(self.alu.b)
- #with m.If(opc_l.q): # XXX operand type in at same time as src1/src2
- m.d.comb += self.alu.op.eq(self.oper_i)
+ m.d.comb += self.busy_o.eq(opc_l.q) # busy out
+ with m.If(req_l.qn & opc_l.q & (self.counter == 0)):
+ m.d.sync += self.counter.eq(5)
+ with m.If(self.counter > 0):
+ m.d.sync += self.counter.eq(self.counter - 1)
+ with m.If((self.counter == 1) | (self.counter == 0)):
+ m.d.comb += self.req_rel_o.eq(req_l.q & opc_l.q) # req release out
+
+ # create a latch/register for src1/src2
+ latchregister(m, self.src1_i, self.alu.a, src_l.q)
+ latchregister(m, self.src2_i, self.alu.b, src_l.q)
+ #with m.If(src_l.qn):
+ # m.d.comb += self.alu.op.eq(self.oper_i)
+
+ # create a latch/register for the operand
+ latchregister(m, self.oper_i, self.alu.op, src_l.q)
+
+ # and one for the output from the ALU
data_o = Signal(self.rwid, reset_less=True) # Dest register
- data_r = Signal(self.rwid, reset_less=True) # Dest register
- with m.If(req_l.q):
- m.d.comb += data_o.eq(self.alu.o)
- m.d.sync += data_r.eq(self.alu.o)
- with m.Else():
- m.d.comb += data_o.eq(data_r)
+ latchregister(m, self.alu.o, data_o, req_l.q)
+
with m.If(self.go_wr_i):
m.d.comb += self.data_o.eq(data_o)