reduce versa_ecp5 clock freq to 50 mhz, reduce bit-width of XICS addressing

[ls2.git] / src / ls2.py

diff --git a/src/ls2.py b/src/ls2.py
index e046a49685654d9e7ad249d67b8a947c672acd9b..50d69e1e5cf337642067fbb82b9a0a22c3c0ec75 100644 (file)
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -312,12 +312,12 @@ class DDR3SoC(SoC, Elaboratable):
             self.int_level_i = self.xics_ics.int_level_i
 
             self.pbus = pbus = wishbone.Interface(name="xics_icp_bus",
-                                         addr_width=10, data_width=32,
+                                         addr_width=6, data_width=32,
                                          granularity=8, features={'stall'})
             self.sbus = sbus = wishbone.Interface(name="xics_ics_bus",
                                          addr_width=10, data_width=32,
                                          granularity=8, features={'stall'})
-            pmap = MemoryMap(addr_width=12, data_width=8, name="icp_map")
+            pmap = MemoryMap(addr_width=8, data_width=8, name="icp_map")
             pbus.memory_map = pmap
             self._decoder.add(pbus, addr=xics_icp_addr) # ICP addr
 
@@ -739,7 +739,7 @@ def build_platform(fpga, firmware):
     if fpga == 'isim':
         clk_freq = 55e6 # below 50 mhz, stops DRAM being enabled
     if fpga == 'versa_ecp5':
-        clk_freq = 55e6 # crank right down to test hyperram
+        clk_freq = 50e6 # crank right down to test hyperram
     if fpga == 'versa_ecp5_85':
         # 50MHz works.  100MHz works.  55MHz does NOT work.
         # Stick with multiples of 50MHz...