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(parent: 96dc900) | patch
reduce versa_ecp5 clock freq to 50 mhz, reduce bit-width of XICS addressing
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 14 Apr 2022 18:45:41 +0000 (19:45 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 14 Apr 2022 18:45:41 +0000 (19:45 +0100)
commit451949c34085f6317c8822e9d596ce97e3bba8a7
tree785c745aaa4ee2e9a0c5442d1a90b5a539506e48tree
parent96dc900e690e68e465b0ef92455935d6bb6bf8a3commit | diff
reduce versa_ecp5 clock freq to 50 mhz, reduce bit-width of XICS addressing
hello_world/Makefile diff | blob | history
hello_world/hello_world.c diff | blob | history
src/ls2.py diff | blob | history